DDR3 50nm lowers cost and power consumption in 2009

New 50nm DDR3 from Samsung and Elpida are entering mass production this month. The chips will feature higher densities and speeds while lowering latencies, power consumption, and costs.

Elpida’s new 50nm process uses 193nm argon fluoride immersion lithography combined with copper interconnect technology, providing a 25 percent speed boost over standard aluminum interconnects. A standard chip size of less than 40mm2 means that there will be more dies produced per wafer, lowering costs once the line matures and yields are maximized.

The new chips are capable of 2.5Gb/s at a standard 1.5v, but can also be used at 1.2v up to 1.6Gb/s. Initial production will be at 1Gb densities. This enables new usage models in the mobile and server application space.

Corsair’s Dominator GT 2GHz CL7 DDR3 DIMMs were shown at CES, and they may enter production this month using Elpida’s latest.

Samsung’s own 50nm process is being used to manufacture 2Gb DDR3, and is expected to become Samsung’s primary DRAM process technology this year. They claim a 60% increase in productivity over their DDR2 equivalents.

Qimonda taped out its 46nm DDR3 Buried Wordline technology in November, ahead of their internal schedule. They hope to start mass production by mid 2009.

Read full story at DailyTech.com

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