You are not registered yet. Please click here to register!
DFI LP UT X48-T3RS - Info, overclocking tips & photos - i4memory.com - different look at memory
Tags Register Blogs FAQ Members List Calendar Mark Forums Read

Notices

Closed Thread
 
Thread Tools
Old 07-06-2008, 07:52 AM   #1
eva2000
Administrator
eva2000's PC Specs
 
Join Date: Jul 22 2004
Location: Brisbane, Australia
Posts: 22,988
twitter.com/i4memorycom Facebook Page livestream.com/i4memorycom
Blog Entries: 42
DFI LP UT X48-T3RS - Info, overclocking tips & photos

DFI LP UT X48-T3RS
Info, overclocking tips & photos

Courtesy of DFI Taiwan, I'll have the opportunity to check out DFI's first DDR3 motherboard, DFI Lanparty UT X48-T3RS based on Intel X48 chipset. I also have the DFI Lanparty UT X48-T2R DDR2 version of the motherboard which I'll be testing as well. This is the review thread while I've setup a dedicated discussion thread here.

[Click thumbnail to view full size photo
- use keyboard arrow keys to cycle through images
- click and hold full size photo to drag and move around]


DFI LP UT X48-T3RS Photos


For DDR2 boards, the only difference between DFI Lanparty UT X48-T2R and Lanparty LT X48-T2R is meant to be that the UT version sports the new Thermalright made heatpipe based heatsink for northbridge, southbridge and mosfet area called Flame Freezer.

The DFI LP UT X48-T3RS DDR3 version also uses the same Flame Freezer heatpipe cooling kit. The kit consists of a 90 degree angled transpiper heatsink to provide additional cooling to mosfet area near I/O connector, a flame freezer heatpipe assembly which cools the northbridge, southbridge and mosfet area and interchangeable northbridge heatsink which can be unclipped and removed so you can replace it with Thermalright's HR-05 series northbridge heatsink.

I decided to fully utilise the additional cooling provided as follows:
  1. Unclip the northbridge heatsink and install my spare Thermalright HR-05 chipset heatsink and used some MX-2 thermal paste to cover the base of the HR-05 heatsink before mounting it via the DFI provided clip to the northbridge heatpipe assembly base.
  2. Install 90 degree transpiper Flame Freezer heatsink, by unscrewing the small retention mounting plate. The manual doesn't mention any use of thermal paste here but I decided to apply a bit of MX-2 to retention mounting plate and then rotated it around the 90 degree transpiper heatpipe to spread the MX-2 before installing.
  3. If you plan on removing the heatpipe assembly, the northbridge and southbridge hole diameters are ~55mm and ~54mm respectively.









More photos here.


Notes: (continually updated)
Downloads:

Beta Bios:
  • 12/24 beta bios - BIOS enhanced the 16GB memory compatibility issue
  • 9/23 beta bios - 1. Added F9 Hot Key function, 2. Fixed ABS function fail when upgrade BIOS, 3. Fixed System cannot display when "two" ATI HD 4870X2 are used in Crossfire, 4. Update Intel new 45nm CPU micro code.
  • 8/29 beta bios - 1. Fixed system can't display when built ATI HD 4870 X2 Cross Fire Edition. 2. Update Intel new 45nm CPU micro code.
  • 8/21 beta bios - 1. Fixed system can't display when insert ATI HD 4870 X2 Graphic card, 2. Added ABS profile version control for UT/LT X38/X48 series.
  • 7/25 beta bios - 1. Fixed system can not display with some Graphic card, 2. Optimized system O.C. function, 3. Fixed on board audio record function, 4. Fixed “Execute Disable Bit” function fail, 5. Fixed USB keyboard fail to hot key to reload CMOS.
  • 7/14 beta bios - 1. Fixed system can not display with some Graphic card, 2. Optimized system O.C. function, 3. Fixed on board audio record function, 4. Fixed “Execute Disable Bit” function fail.
  • 6/27 beta bios - Improved G.Skill Memory compatibility issue.
  • 6/20 beta bios - Improved Memory compatibility & Enhance system OC function.
  • 6/9 beta bios - visually I only see the 6 MCH GTL Ref voltages being removed. Everything else looks like 6/4 beta within bios.
Official Bios:
Other DFI Lanparty UT X48-T3RS Reviews

Last edited by eva2000; 23-01-2009 at 01:13 PM.
eva2000 is offline  
Old 07-06-2008, 07:53 AM   #2
eva2000
Administrator
eva2000's PC Specs
 
Join Date: Jul 22 2004
Location: Brisbane, Australia
Posts: 22,988
twitter.com/i4memorycom Facebook Page livestream.com/i4memorycom
Blog Entries: 42
DFI LP UT X48-T3RS Bios Screenshots & Template

6/4 Beta Bios Screenshots

Received the 6/4 beta bios. There's 2 versions one is particularly optimised for clock fine delay values suited to Micron D9 DDR3 memory modules. This is the one I flashed to.

Visible changes:
[Click thumbnail to view full size photo
- use keyboard arrow keys to cycle through images
- click and hold full size photo to drag and move around]








More screenshots here


5/21 Official Bios Screenshots


[Click thumbnail to view full size photo
- use keyboard arrow keys to cycle through images
- click and hold full size photo to drag and move around]








More screenshots here


DFI LP UT X48-T3RS Bios Settings Template


6/4 beta bios

Code:
PC Health Status
Adjust CPU Temp: Auto

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
O.C. Fail retry Counter 0
CPU Clock Ratio: 9x
CPU N/2 Ratio: Disabled
Target CPU Clock:
CPU Clock: 333
Boot Up Clock: AUTO
CPU Clock Amplitude: 800mv
CPU Clock0 Skew: 0ps
CPU Clock1 Skew: 0ps
DRAM Speed: 333/1333
- Target DRAM Speed: DDR3-1333
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.10000v
COY VID Special Add Limit: Enabled
CPU VID Special Add: AUT0
DRAM Voltage Control: 1.57v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.430
CPU VTT Voltage: 1.100
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
x MCH RON Offset Value:
x MCH RTT Offset Value:
x MCH Slew Rate Offset Value:
x MCH VREF 1 Value:
x MCH VREF 2 Value: 
x MCH VREF 3 Value:

GTL REF Voltage Control: Disable
x CPU GTL 1/2 REF Volt: 113
x CPU GTL 0/3 REF Volt: 100
x North Bridge GTL REF Volt: 100

DRAM Timing
- Enhance Data transmitting: Auto
- Enhance Addressing: Auto
- T2 Dispatch: Auto

DRAM Default Skew Model: Model 0 to 3

Fine Delay Step Degree: 5ps to 80ps

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: AUTO
- DIMM 1 Clock fine delay: Current
- DIMM 2 Clock fine delay: Current
- DIMM 2 Control fine delay: Current
- DIMM 1 Control fine delay: Current
- Ch 1 Command fine delay: Current

Ch2 Clock Crossing Setting: AUTO
- DIMM 3 Clock fine delay: Current
- DIMM 4 Clock fine delay: Current
- DIMM 4 Control fine delay: Current
- DIMM 3 Control fine delay: Current
- Ch 2 Command fine delay: Current

Ch1Ch2 CommonClock Setting: AUTO

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

Common CMD to CS Timing: AUTO/1N/2N (command rate)

CAS Latency Time (tCL): 8
RAS# to CAS# Delay (tRCD): 8
RAS# Precharge (tRP): 8
Precharge Delay (tRAS): 27
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): Auto
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO
- Channel 1 Phase 1 Pull-In: AUTO
- Channel 1 Phase 2 Pull-In: AUTO
- Channel 1 Phase 3 Pull-In: AUTO
- Channel 1 Phase 4 Pull-In: AUTO

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

DFI LP UT X48-T3RS Bios Settings Template


5/21 official bios

Code:
PC Health Status
Adjust CPU Temp: Auto

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
O.C. Fail retry Counter 0
CPU Clock Ratio: 9x
CPU N/2 Ratio: Disabled
Target CPU Clock:
CPU Clock: 333
Boot Up Clock: AUTO
CPU Clock Amplitude: 800mv
CPU Clock0 Skew: 0ps
CPU Clock1 Skew: 0ps
DRAM Speed: 333/1333
- Target DRAM Speed: DDR3-1333
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.10000v
COY VID Special Add Limit: Enabled
CPU VID Special Add: AUT0
DRAM Voltage Control: 1.57v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.430
CPU VTT Voltage: 1.100
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL 1/2 REF Volt: 110
x CPU GTL 0/3 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: Auto
- Enhance Addressing: Auto
- T2 Dispatch: Auto

DLL Mode: Mode 0

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: AUTO
- DIMM 1 Clock fine delay: Current
- DIMM 2 Clock fine delay: Curren
- DIMM 1 Control fine delay: Current
- DIMM 2 Control fine delay: Current
- Ch 1 Command fine delay: Current

Ch2 Clock Crossing Setting: AUTO
- DIMM 3 Clock fine delay: Current
- DIMM 4 Clock fine delay: Current
- DIMM 3 Control fine delay: Current
- DIMM 4 Control fine delay: Current
- Ch 2 Command fine delay: Current

Ch1Ch2 CommonClock Setting: AUTO

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

CAS Latency Time (tCL): 8
RAS# to CAS# Delay (tRCD): 8
RAS# Precharge (tRP): 8
Precharge Delay (tRAS): 27
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): Auto
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO
- Channel 1 Phase 1 Pull-In: AUTO
- Channel 1 Phase 2 Pull-In: AUTO
- Channel 1 Phase 3 Pull-In: AUTO
- Channel 1 Phase 4 Pull-In: AUTO

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO
CMD to CST mode: AUTO/1T/2T

Last edited by eva2000; 12-06-2008 at 10:53 AM.
eva2000 is offline  
Old 07-06-2008, 07:54 AM   #3
eva2000
Administrator
eva2000's PC Specs
 
Join Date: Jul 22 2004
Location: Brisbane, Australia
Posts: 22,988
twitter.com/i4memorycom Facebook Page livestream.com/i4memorycom
Blog Entries: 42
DFI LP UT X48-T3RS Voltage Measure Points - digital multimeter

DFI LP UT X48-T3RS Voltage Measure Points
provided by DFI

Thanks to Jimmy at DFI for the images and info

[Click below links to view full size photo
- use keyboard arrow keys to cycle through images
- click and hold full size photo to drag and move around]


Last edited by eva2000; 12-06-2008 at 10:55 AM.
eva2000 is offline  
Old 07-06-2008, 08:03 AM   #4
eva2000
Administrator
eva2000's PC Specs
 
Join Date: Jul 22 2004
Location: Brisbane, Australia
Posts: 22,988
twitter.com/i4memorycom Facebook Page livestream.com/i4memorycom
Blog Entries: 42
Memory Testing 5/21 official bios - DFI LP UT X48-T3RS

System specs
  • Intel Core 2 Duo E8500 Q740A493T
  • Corsair Nautilus 500
  • DFI LP UT X48-T3RS 5/21 bios
  • 128MB Gainward FX5200 PCI
  • 2x1GB OCZ PC3-14400 Platinum dual channel kit cooled by 3x 60x25mm Sunon 23.5cfm MagLev fans.
  • 750GB Samsung HD753LJ
  • Pioneer DVD-RW
  • 620W Corsair HX620
  • WinXP Pro SP2

Memory testing

Max FSB etc tests will have to wait until I figure out the memory side of things since it can effect max FSB too

There's meant to be a much improved 6/4 beta bios out there, but for now I'll have to make do with 5/21 shipping bios. Update 9/06/08: I've gotten my hands on 6/4 beta bios, so will do more testing since 6/4 added additional DRAM Default Skew Models to work with.

Notes:
  • Board seems to default to 1T command rate when CMD to CST mode option is set to AUTO.
  • Smart Guardian seems to over report vdimm set in bios by ~0.02v - have yet to measure actual vdimm using a multimeter.
  • My 2x1GB Cellshock PC3-14400 kit doesn't seem to want to boot with 5/21 shipping bios - could be the older DDR3-1800 SPD on them, as newer kits apparently have DDR3-1600 SPD or just 5/21 bios related ? Will wait for 6/4 bios to find out.
  • The memory dividers need some work i.e. 3:5 (400/1333) divider when set with E8500 cpu in place actually turns out to be 2:3 real divider. Update: according to DFI RD, the 400/1333 should actually be listed as 400/1200 so 2:3 divider is correct - it appears 400/1333 is 3:5 divider just I think performance isn't as high as I expect it to be.
  • I can confirm, that dimm slot 2+4 yellow slots are indeed better for memory overclocking and thus for max FSB at strap/divider. For example, at 333/1333 divider max FSB frequency rose from green dimm 1+3 slot 380FSB cap to 433FSB dimm 2+4 slot before needing to use 400/1600 divider. Apparently, since a bit low as some folks are doing 485-500FSB on 333/1333 divider - probably influenced by how good your DDR3 modules are ?
  • Under Read Delay Phase Adjust menu options, there's a DLL Mode option for mode 0 and mode 1. Seems for my OCZ PC3-14400 Platinum memory (11 month old review sample) once I hit up to 940Mhz memory frequency, mode 1 seems more more stable. Not sure what the DLL mode does, but might be for different memory types/densities/profiles for better compatibility ?
  • Clock fine delay tweaking works the same as DFI P35/X38 boards as outlined here. Although, up to 470FSB 1:2 940Mhz, I haven't had to tweak or adjust their values while in dimm 2+4 yellow slots. I did have to adjust them slightly when I used dimm 1+3 green slots.
  • OCZ PC3-14400 Platinum memory isn't clocking as tight as they did on Asus Blitz Extreme from brief (<12hrs) of testing. On Asus Blitz Extreme got the memory to 960Mhz max CAS8 frequency with 950Mhz 7-7-7-18 at 2.28v Super Pi 32M capable. They also did 6-6-6-x upto around 864Mhz. So far on DFI LP UT X48-T3RS, max frequency around 970Mhz with me only getting tightest at 940-950Mhz 8-7-6-18/21 at 2.15-2.22v. 6-6-6-x results in no boot even at 666Mhz speeds. Hopefully, 6/4 beta bios will improve on this

Looking at some <4000Mhz super pi 32M efficiency results below they seem pretty good for the FSB used @470FSB for 8-7-6-21 and 8-7-6-18 timings at 2.15v and 2.22v vdimm respectively. The OCZ PC3-14400 Platinum need alot more vdimm for tighter tRAS which is a characteristic of this set since day one I got them (11 months ago).

Super Pi 32M untweaked times
  • @3996Mhz - 470FSB / 940Mhz 8-7-6-21 1T at 2.15v = 11m 16.422s
  • @3996Mhz - 470FSB / 940Mhz 8-7-6-18 1T at 2.22v = 11m 12.219s

Bios settings used for 940Mhz 8-7-6-18 1T run only differed from 8-7-6-21 1T run by changing options in bold from Fast-Fast-Enabled to Fast-Auto-Disabled:

Code:
DFI LP UT X48-T3RS Bios Settings
PC Health Status Adjust CPU Temp: Auto CPU Feature - Thermal Management Control: Disabled - PPM(EIST) Mode: Disabled - Limit CPUID MaxVal: Disabled - CIE Function: Disabled - Virtualization Technology: Disabled - Core Multi-Processing: Enabled Exist Setup Shutdown: Mode 2 Shutdown after AC Loss: Disabled O.C. Fail retry Counter 0 CPU Clock Ratio: 8.5x CPU N/2 Ratio: Enabled Target CPU Clock: CPU Clock: 470 Boot Up Clock: AUTO CPU Clock Amplitude: 800mv CPU Clock0 Skew: 200ps CPU Clock1 Skew: 200ps DRAM Speed: 400/1600 - Target DRAM Speed: DDR3-1880 PCIE Clock: 100mhz PCIE Slot Config: 1X 1X CPU Spread Spectrum: Disabled PCIE Spread Spectrum: Disabled SATA Spread Spectrum: Disabled Voltage Settings CPU VID Control: 1.33750v COY VID Special Add Limit: Enabled CPU VID Special Add: AUT0 DRAM Voltage Control: 2.220v SB Core/CPU PLL Voltage: 1.51 NB Core Voltage: 1.643 CPU VTT Voltage: 1.200 Vcore Droop Control: Enabled Clockgen Voltage Control: 3.45v GTL+ Buffers Strength: Strong Host Slew Rate: Weak GTL REF Voltage Control: Disable x CPU GTL1/3 REF Volt: 110 x CPU GTL 0/2 REF Volt: 110 x North Bridge GTL REF Volt: 110 DRAM Timing - Enhance Data transmitting: FAST - Enhance Addressing: FAST - T2 Dispatch: Enabled DLL Mode: Mode 1 Clock Setting Fine Delay Ch1 Clock Crossing Setting: AUTO - DIMM 1 Clock fine delay: Current 245 - DIMM 2 Clock fine delay: Current 245 - DIMM 1 Control fine delay: Current 168 - DIMM 2 Control fine delay: Current 168 - Ch 1 Command fine delay: Current 189 Ch2 Clock Crossing Setting: AUTO - DIMM 3 Clock fine delay: Current 1052 - DIMM 4 Clock fine delay: Current 427 - DIMM 3 Control fine delay: Current 273 - DIMM 4 Control fine delay: Current 274 - Ch 2 Command fine delay: Current 189 Ch1Ch2 CommonClock Setting: AUTO Ch1 RDCAS GNT-Chip Delay: Auto Ch1 WRCAS GNT-Chip Delay: Auto Ch1 Command to CS Delay: Auto Ch2 RDCAS GNT-Chip Delay: Auto Ch2 WRCAS GNT-Chip Delay: Auto Ch2 Command to CS Delay: Auto CAS Latency Time (tCL): 8 RAS# to CAS# Delay (tRCD): 7 RAS# Precharge (tRP): 6 Precharge Delay (tRAS): 18 All Precharge to Act: AUTO REF to ACT Delay (tRFC): 52 Performance LVL (Read Delay) (tRD): 7 Read delay phase adjust: Enter Ch1 Read delay phase (4~0) - Channel 1 Phase 0 Pull-In: AUTO - Channel 1 Phase 1 Pull-In: AUTO - Channel 1 Phase 2 Pull-In: AUTO - Channel 1 Phase 3 Pull-In: AUTO - Channel 1 Phase 4 Pull-In: AUTO Ch2 Read delay phase (4~0) - Channel 2 Phase 0 Pull-In: Auto - Channel 2 Phase 1 Pull-In: Auto - Channel 2 Phase 2 Pull-In: Auto - Channel 2 Phase 3 Pull-In: Auto - Channel 2 Phase 4 Pull-In: Auto MCH ODT Latency: AUTO Write to PRE Delay (tWR): AUTO Rank Write to Read (tWTR): AUTO ACT to ACT Delay (tRRD): AUTO Read to Write Delay (tRDWR): AUTO Ranks Write to Write (tWRWR): AUTO Ranks Read to Read (tRDRD): AUTO Ranks Write to Read (tWRRD): AUTO Read CAS# Precharge (tRTP): AUTO ALL PRE to Refresh: AUTO CMD to CST mode: AUTO defaults to 1T

Last edited by eva2000; 17-08-2008 at 03:02 AM.
eva2000 is offline  
Old 07-06-2008, 08:03 AM   #5
eva2000
Administrator
eva2000's PC Specs
 
Join Date: Jul 22 2004
Location: Brisbane, Australia
Posts: 22,988
twitter.com/i4memorycom Facebook Page livestream.com/i4memorycom
Blog Entries: 42
6/4 Beta Bios - Memory testing - DFI LP UT X48-T3RS

6/4 Beta Bios - Memory testing continued

I've flashed to 6/4 beta bios and it has opened up memory clocking quite a bit with the help of DRAM Default Skew model options. Before with 5/21 official bios, this 2x1GB OCZ PC3-14400 Platinum was struggling to pass 970Mhz 8-8-8-24 at 2.15-2.22v and no way it would boot into windows >970Mhz. Now with 6/4 beta bios and DRAM Default Skew set to Model 3 (tuned for Micron D9 ICs), I managed to pull off 1M @1010Mhz 8-7-6-24 at 2.15v and max cpuz validation @1040Mhz 8-7-6-24 at 2.15v !

It seems that DRAM Default Skew model options have really opened up a world of possibilities regarding memory overclocking tailored to different IC types

DFI LP UT X48-T3RS 6/4 Beta Bios Settings

Code:
PC Health Status
Adjust CPU Temp: Auto

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
O.C. Fail retry Counter 0
CPU Clock Ratio: 8x
CPU N/2 Ratio: Disabled
Target CPU Clock:
CPU Clock: 505
Boot Up Clock: AUTO
CPU Clock Amplitude: 900mv
CPU Clock0 Skew: 900ps
CPU Clock1 Skew: 900ps
DRAM Speed: 333/1333
- Target DRAM Speed: DDR3-1333
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.38750v
COY VID Special Add Limit: Enabled
CPU VID Special Add: AUT0
DRAM Voltage Control: 2.15v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.655
CPU VTT Voltage: 1.300
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
x MCH RON Offset Value:
x MCH RTT Offset Value:
x MCH Slew Rate Offset Value:
x MCH VREF 1 Value:
x MCH VREF 2 Value: 
x MCH VREF 3 Value:

GTL REF Voltage Control: Disable
x CPU GTL 1/2 REF Volt: 113
x CPU GTL 0/3 REF Volt: 100
x North Bridge GTL REF Volt: 100

DRAM Timing
- Enhance Data transmitting: Auto
- Enhance Addressing: Auto
- T2 Dispatch: Auto

DRAM Default Skew Model: Model 3

Fine Delay Step Degree: 5ps to 80ps

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: AUTO
- DIMM 1 Clock fine delay: Current 294ps
- DIMM 2 Clock fine delay: Curren 294ps
- DIMM 2 Control fine delay: Current 420ps
- DIMM 1 Control fine delay: Current 532ps
- Ch 1 Command fine delay: Current 623ps

Ch2 Clock Crossing Setting: AUTO
- DIMM 3 Clock fine delay: Current 511ps
- DIMM 4 Clock fine delay: Current 511ps
- DIMM 4 Control fine delay: Current 77ps
- DIMM 3 Control fine delay: Current 189ps
- Ch 2 Command fine delay: Current 280ps

Ch1Ch2 CommonClock Setting: AUTO

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

Common CMD to CS Timing: /2N (command rate)

CAS Latency Time (tCL): 8
RAS# to CAS# Delay (tRCD): 7
RAS# Precharge (tRP): 6
Precharge Delay (tRAS): 24
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): 60
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO
- Channel 1 Phase 1 Pull-In: AUTO
- Channel 1 Phase 2 Pull-In: AUTO
- Channel 1 Phase 3 Pull-In: AUTO
- Channel 1 Phase 4 Pull-In: AUTO

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

More tests to come...

Last edited by eva2000; 12-06-2008 at 10:52 AM.
eva2000 is offline  
Old 07-06-2008, 08:03 AM   #6
eva2000
Administrator
eva2000's PC Specs
 
Join Date: Jul 22 2004
Location: Brisbane, Australia
Posts: 22,988
twitter.com/i4memorycom Facebook Page livestream.com/i4memorycom
Blog Entries: 42
6/9 Beta bios - Memory testing -DFI LP UT X48-T3RS

6/9 Beta bios - Memory testing

DFI released a 6/9 beta bios which is meant to improve memory overclocking. Visually not many changes compared to 6/4 beta bios except the removal of 6 of the MCH GTL ref options. With 6/9 beta bios I can't hit 8x500FSB 400/1600 DDR3-2000Mhz at all = no boot - on 6/4 TTTT.bin beta bios I could using model 3 though. I tried all 4 models from 0 to 3 and none allow me to boot at 8x500 400/600 on 6/9 beta bios.

However, 6/9 beta bios has improved memory overclocking in general especially on 7-7-7-x timings. I managed to complete both single Super Pi 32M and dual Super Pi 32M via HyperPi gui wrapper app @934Mhz 7-7-7-18 1T at 2.15v again DRAM Default Skew model 3 helped stabilize my Micron D9 IC based 2x1GB OCZ PC3-14400 Platinum kit along with a slight adjustment for DIMM 4 Clock fine delay changing it from Current 462ps to 22 DEG 550ps with a Fine Delay Step Degree value of 25ps (22x25ps = 550ps)

@934Mhz 7-7-7-18 1T at 2.15v



Result:
@940Mhz 7-7-7-18 1T at 2.15v

Bit higher at same 2.15v vdimm. Nearly pulled off 950Mhz 7-7-7-18 1T at 2.15v but errored out half way into Super Pi 32M

Result:

DFI LP UT X48-T3RS Bios Settings

6/9 beta bios

Code:
PC Health Status
Adjust CPU Temp: Auto

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
O.C. Fail retry Counter 0
CPU Clock Ratio: 8x
CPU N/2 Ratio: Disabled
Target CPU Clock: 3736
CPU Clock: 467
Boot Up Clock: AUTO
CPU Clock Amplitude: 800mv
CPU Clock0 Skew: 200ps
CPU Clock1 Skew: 200ps
DRAM Speed: 400/1600
- Target DRAM Speed: DDR3-1868
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.250v
COY VID Special Add Limit: Enabled
CPU VID Special Add: AUT0
DRAM Voltage Control: 2.15v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.677
CPU VTT Voltage: 1.240
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL 1/2 REF Volt: 113
x CPU GTL 0/3 REF Volt: 100
x North Bridge GTL REF Volt: 100

DRAM Timing
- Enhance Data transmitting: Auto
- Enhance Addressing: Auto
- T2 Dispatch: Auto

DRAM Default Skew Model: Model 3

Fine Delay Step Degree: 25ps

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: AUTO
- DIMM 1 Clock fine delay: Current 350ps
- DIMM 2 Clock fine delay: Curren 350ps
- DIMM 2 Control fine delay: Current 385ps
- DIMM 1 Control fine delay: Current 385ps
- Ch 1 Command fine delay: Current 203ps

Ch2 Clock Crossing Setting: AUTO
- DIMM 3 Clock fine delay: Current 462ps
- DIMM 4 Clock fine delay: 22 DEG 550ps
- DIMM 4 Control fine delay: Current 490ps
- DIMM 3 Control fine delay: Current 490ps
- Ch 2 Command fine delay: Current 315ps

Ch1Ch2 CommonClock Setting: AUTO

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

Common CMD to CS Timing: Auto = 1T

CAS Latency Time (tCL): 7
RAS# to CAS# Delay (tRCD): 7
RAS# Precharge (tRP): 7
Precharge Delay (tRAS): 18
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): 56
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO
- Channel 1 Phase 1 Pull-In: AUTO
- Channel 1 Phase 2 Pull-In: AUTO
- Channel 1 Phase 3 Pull-In: AUTO
- Channel 1 Phase 4 Pull-In: AUTO

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO
@950Mhz 7-7-7-18 1T at 2.22v

Bumped voltages up but kept timings all the same for DDR3-1900Mhz 7-7-7-18 1T at 2.22v for single Super Pi 32M run


Results
DFI LP UT X48-T3RS Bios Settings

6/9 beta bios

Code:
PC Health Status
Adjust CPU Temp: Auto

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
O.C. Fail retry Counter 0
CPU Clock Ratio: 8x
CPU N/2 Ratio: Disabled
Target CPU Clock: 3802
CPU Clock: 475
Boot Up Clock: AUTO
CPU Clock Amplitude: 800mv
CPU Clock0 Skew: 300ps
CPU Clock1 Skew: 300ps
DRAM Speed: 400/1600
- Target DRAM Speed: DDR3-1900
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.2750v
COY VID Special Add Limit: Enabled
CPU VID Special Add: AUT0
DRAM Voltage Control: 2.22v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.677
CPU VTT Voltage: 1.270
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL 1/2 REF Volt: 113
x CPU GTL 0/3 REF Volt: 100
x North Bridge GTL REF Volt: 100

DRAM Timing
- Enhance Data transmitting: Auto
- Enhance Addressing: Auto
- T2 Dispatch: Auto

DRAM Default Skew Model: Model 3

Fine Delay Step Degree: 25ps

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: AUTO
- DIMM 1 Clock fine delay: Current 350ps
- DIMM 2 Clock fine delay: Curren 350ps
- DIMM 2 Control fine delay: Current 385ps
- DIMM 1 Control fine delay: Current 385ps
- Ch 1 Command fine delay: Current 203ps

Ch2 Clock Crossing Setting: AUTO
- DIMM 3 Clock fine delay: Current 462ps
- DIMM 4 Clock fine delay: 22 DEG 550ps
- DIMM 4 Control fine delay: Current 490ps
- DIMM 3 Control fine delay: Current 490ps
- Ch 2 Command fine delay: Current 315ps

Ch1Ch2 CommonClock Setting: AUTO

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

Common CMD to CS Timing: Auto = 1T

CAS Latency Time (tCL): 7
RAS# to CAS# Delay (tRCD): 7
RAS# Precharge (tRP): 7
Precharge Delay (tRAS): 18
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): 56
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO
- Channel 1 Phase 1 Pull-In: AUTO
- Channel 1 Phase 2 Pull-In: AUTO
- Channel 1 Phase 3 Pull-In: AUTO
- Channel 1 Phase 4 Pull-In: AUTO

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO


@1002Mhz 7-7-7-18 1T at 2.22v

Boot from 950Mhz 7-7-7-18 1T at 2.22v and setFSB my way up to max CPUZ Validation of DDR3-2004Mhz 1T at 2.22v


Result:
Max CPUZ Validation = 1002Mhz 7-7-7-18 1T at 2.22v

Last edited by eva2000; 12-06-2008 at 10:52 AM.
eva2000 is offline  
Old 07-06-2008, 08:04 AM   #7
eva2000
Administrator
eva2000's PC Specs
 
Join Date: Jul 22 2004
Location: Brisbane, Australia
Posts: 22,988
twitter.com/i4memorycom Facebook Page livestream.com/i4memorycom
Blog Entries: 42
DFI LP UT X48-T3RS - 2x 512MB HIS IceQ3 Turbo HD3850 Crossfire

DFI Lanparty UT X48-T3RS
+
2x 512MB HIS IceQ 3 Turbo HD3850 Crossfire

Now that I have a better understand of how memory works on this motherboard, time to fully load up the motherboard with 2x 512MB HIS IceQ3 Turbo HD3850 in Crossfire.

Notes:
  • As you can see the PCI-E slot spacing required DFI to include with their accessories a longer Crossfire bridge connector cable.
  • There's still ample room to reach the the power and reset connectors even with double slot with video card coolers
  • The fan header connector near the 1st set of SATA ports is still accessible as well

[Click thumbnail to view full size photo
- use keyboard arrow keys to cycle through images
- click and hold full size photo to drag and move around]





More photos here.

System specs
Interesting discovery when I installed Catalyst 8.5 drivers, CCC complained that CrossfireX is disabled and can't be enabled and for me to check the crossfire connector bridge was connected properly. It turns out from the above photos you can see I installed the crossfire connector bridge on the connectors closest to the PCI retention plate. This is in fact incorrect. You need to install the crossfire connector bridge on the other connectors pictured here.

When crossfire connector bridge is installed in wrong connector slots you see the following (click image for full version):



When crossfire connector bridge is correctly installed:




Results (without LOD tweaks):

E8500 @9x445FSB = 4008Mhz
2x512MB HD3850 CF stock @715/909


E8500 @9x467FSB = 4203Mhz
2x512MB HD3850 CF stock @715/909


E8500 @9x467FSB = 4203Mhz
2x512MB HD3850 CF @810/999


First time using Cat 8.5 drivers, so not sure why I can't clock my HIS HD3850 CF setup past 810Mhz GPU core, as both rivatuner 2.09 and GPUZ report 810mhz GPU even though I set GPU to 815mhz or 820mhz (resulted in same score as 810mhz) ?

Update: July 27, 2008
New 714 beta bios with new set of memory and Cat 8.5 vs 8.7 3dmark results.

System specs
  • Intel Core 2 Duo E8500 Q740A493T
  • Corsair Nautilus 500
  • DFI LP UT X48-T3RS 714 Beta bios
  • 2x512MB HIS IceQ3 Turbo HD3850 CF @810/1000 Cat 8.5 & 8.7
  • 2x1GB G.Skill F3-12800CL7D 2GB HZ Micron D9JNM
  • 750GB Samsung HD753LJ
  • Pioneer DVD-RW
  • 620W Corsair HX620
  • WinXP Pro SP2

3Dmark: Cat 8.5 / Cat 8.7
3dmark2001: 74,770 / 74,641
3dmark2003: 70,123 / 70,338
3dmark05: 27,445 / 27,445
3dmark06: 18,509 / 18,517

Last edited by eva2000; 27-07-2008 at 04:50 AM.
eva2000 is offline  
Old 07-06-2008, 08:04 AM   #8
eva2000
Administrator
eva2000's PC Specs
 
Join Date: Jul 22 2004
Location: Brisbane, Australia
Posts: 22,988
twitter.com/i4memorycom Facebook Page livestream.com/i4memorycom
Blog Entries: 42
Re: DFI LP UT X48-T3RS - Info, overclocking tips & photos

Currently testing a few beta bioses with my 2x1GB OCZ PC3-14400 Platinum and 2x1GB Cellshock PC3-14400 (yes they now boot) and while I am still testing, I'd thought I'd list a few tips for new DFI LP UT X48-T3RS users gained from my experience
  1. Yellow dimm 2+4 slots clock memory better than Green dimm 1+3 slots
  2. Always when testing settings etc, boot into memtest86+ v2.01 first. 1000s of errors in memtest86+ v2.01 don't necessarily mean memory is faulty but you may have incorrect voltages, timings or settings set for your config but booting into memtest would save you hassle of corrupting your operating system.
  3. Latest beta bioses have improved the board alot compared to shipping bios! So grabbing latest beta bios (currently 8/29 official bios is best) is recommended especially from 6/27 and up.
  4. When first testing for max FSB or dividers, timings (particularly CAS timing), probably best to stick with 400/1600 (1:2) divider and set tRD performance level to a high number i.e. 9 and above. You can always dial down and tighten tRD performance level along with phase adjustments later on once you figure out the settings etc. This will eliminate a few factors such as too tight performance level at certain FSB ranges i.e. >480FSB. As well as eliminate the bios trying to set tRD performance level in line with your CAS timing set. For example 7-7-7-21 timings and 8-8-8-24 timings would set tRD performance level to 7 and 8 respectively if tRD was left on AUTO instead of manual value of 9 and above. At >480FSB, you'd run in to troubles if you left tRD on AUTO with CAS 6 or 7 unless you shoved alot of NB volts in.
  5. Play with DDRAM Default skew models under Clock Fine Delay menu as each model is tailored to different types of memory modules. From 6/27 beta bios and up there's 8 models to play with from model 0 to 7. Find the model that clocks your memory the best. 8/29 official bios has improved this aspect from various memory i tested at least decently boot/work with model 0, which will allow you to boot up and use memtest86+ v2.01 and windows stability tests to figure out which model from 0 to 7 will give your memory the best mileage in terms of overclock and stability and amount of memory voltage needed.
  6. Recovering from failed clocks is easy. Power off system, and wait 30-60 seconds then boot up while holding down the Home key - if you want to boot at cpu default FSB, or while holding down Insert key if you want to boot with default reset settings. I find the Home key much more useful. If that doesn't work, clear cmos using either Ez Clear on page 11 of manual or usual clear cmos jumper on page 10 of manual.

Last edited by eva2000; 27-09-2008 at 01:05 PM.
eva2000 is offline  
Closed Thread

Bookmarks

Tags
ddr3, dfi, dfi overlocking, dfi photos, dfi tweaks, lanparty, ut x48-t3rs, x48


Currently Active Users Viewing This Thread: 1 (0 members and 1 guests)
 
Thread Tools


Similar Threads for: DFI LP UT X48-T3RS - Info, overclocking tips & photos
Thread Thread Starter Forum Replies Last Post
DFI Lanparty DK X48-T2RBS Plus bios, info, photos & overclocking tips eva2000 DFI Intel Motherboard / CPU 159 10-09-2012 06:40 AM
DFI LP UT X48-T3RS - Info, overclocking tips & photos - discussions eva2000 DFI Intel Motherboard / CPU 28 26-09-2008 08:07 PM
DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] eva2000 DFI Intel Motherboard / CPU 82 08-05-2008 04:28 AM
AMD64 Overclocking Guide (07/11/06) eva2000 General AMD Motherboards / CPU 7 02-11-2006 04:42 PM


All times are GMT +11. The time now is 03:01 AM.

no new posts