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Old 28-08-2007, 04:18 PM   #1
eva2000
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Join Date: Jul 22 2004
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Talking DFI LP UT P35-T2R bios templates

19/09/08 Bios template:


Use this template to share your DFI UT P35-T2R bios settings

CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio:
CPU N/2 Ratio: Disabled
- Target CPU Clock:
CPU Clock:
Boot Up Clock:
DRAM Speed:
- Target DRAM Speed:
PCIE Clock: 100mhz

Voltage Settings
CPU VID Control:
CPU VID Special Add:
DRAM Voltage Control:
SB 1.05V Voltage:
SB Core/CPU PLL Voltage:
NB Core Voltage:
CPU VTT Voltage:
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: AUTO (Turbo needs high NB volts)
- Enhance Addressing: AUTO
- T2 Dispatch: Disabled (Disable for better memory stability)

Clock Setting Fine Delay
Tfine Item Value Degree: 70ps (10ps to 160ps range)

Ch1 Clock Crossing Setting: Aggressive for better performance, Relax for stability
- DIMM 1 CLK fine delay: Current
- DIMM 2 CLK fine delay: Current
- Ch 1 Command fine delay: Current
- Ch 1 Control fine delay: Curent

Ch2 Clock Crossing Setting: Aggressive for better performance, Relax for stability
- DIMM 3 CLK fine delay: Current
- DIMM 4 CLK fine delay: Current
- Ch 2 Command fine delay: Current
- Ch 2 Control fine delay: Curent

Ch1Ch2 CommonClock Setting: Auto

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)

CAS Latency Time (tCL):
RAS# to CAS# Delay (tRCD):
RAS# Precharge (tRP):
Precharge Delay (tRAS):
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter
- Channel 1 Phase 0 Pull-In: Auto (each Phase when enabled = (Common tRD - 1)
- Channel 1 Phase 1 Pull-In: Auto
- Channel 1 Phase 2 Pull-In: Auto
- Channel 1 Phase 3 Pull-In: Auto
- Channel 1 Phase 4 Pull-In: Auto

- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 6
Ranks Read to Read (tRDRD): 6
Ranks Write to Read (tWRRD): 5
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

13/09/07 Bios template:


9/13 bios download http://us.dfi.com.tw/Support/Downloa...FLAG=A&SITE=US

Code:
Major Reasons of Change:
1.Enhance data transmitting added turbo.
2.Fixed cdrom name error in setup.
3.Added CMD Tfine control Tfine Item.
4.Added Tras 1~8.
5.Added T2 Dispatch item.
6.Change Read delay phase adjust item config.
Code:
CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio:
- Target CPU Clock:
CPU Clock:
Boot Up Clock:
DRAM Speed:
- Target DRAM Speed:
PCIE Clock: 100mhz

Voltage Settings
CPU VID Control:
CPU VID Special Add:
DRAM Voltage Control:
SB 1.05V Voltage:
SB Core/CPU PLL Voltage:
NB Core Voltage:
CPU VTT Voltage:
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: AUTO (Turbo needs high NB volts)
- Enhance Addressing: AUTO
- T2 Dispatch: Disabled (Disable for better memory stability)

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: Aggressive for better performance, Relax for stability
- DIMM 1 CLK fine delay: Current (increasing delay by 1 or 2 & decrease Command/Control delay by 1 or 2 may help 1T/2T oc'ing)
- DIMM 2 CLK fine delay: Current
- Ch 1 Command fine delay: Current
- Ch 1 Control fine delay: Curent

Ch2 Clock Crossing Setting: Aggressive for better performance, Relax for stability
- DIMM 3 CLK fine delay: Current (increasing delay by 1 or 2 & decrease Command/Control delay by 1 or 2 may help 1T/2T oc'ing)
- DIMM 4 CLK fine delay: Current
- Ch 2 Command fine delay: Current
- Ch 2 Control fine delay: Curent

Ch1Ch2 CommonClock Setting: Auto

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)

CAS Latency Time (tCL): 
RAS# to CAS# Delay (tRCD):
RAS# Precharge (tRP):
Precharge Delay (tRAS):
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter
- Channel 1 Phase 0 Pull-In: Auto (each Phase when enabled = (Common tRD - 1)
- Channel 1 Phase 1 Pull-In: Auto
- Channel 1 Phase 2 Pull-In: Auto
- Channel 1 Phase 3 Pull-In: Auto
- Channel 1 Phase 4 Pull-In: Auto

- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled
23/08/07 Bios template:


8/23 bios download http://us.dfi.com.tw/Support/Downloa...FLAG=A&SITE=US

Change log:
Code:
Major Reasons of Change:
1. Added LAN, Audio,1394, IDE chip Item.
2. Support DDR2 533 Module when NB strap jump set to 333MHz.
3. Fixed can't install vista when plus 4GB memory.
4. Fixed Vista64 DRAM size issue.
5. Fixed EIST can't be disabled in vista.
6. Fixed can't boot from SATA CD-ROM when Enable RAID mode..
Use this template to share your DFI UT P35-T2R bios settings

Code:
CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio:
- Target CPU Clock:
CPU Clock:
Boot Up Clock:
DRAM Speed:
- Target DRAM Speed:
PCIE Clock: 100mhz

Voltage Settings
CPU VID Control:
CPU VID Special Add:
DRAM Voltage Control:
SB 1.05V Voltage:
SB Core/CPU PLL Voltage:
NB Core Voltage:
CPU VTT Voltage:
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: AUTO
- Enhance Addressing: AUTO
- DIMM 1 CLK fine delay: Current
- DIMM 2 CLK fine delay: Current
- DIMM 3 CLK fine delay: Current
- DIMM 4 CLK fine delay: Current

CAS Latency Time (tCL): 
RAS# to CAS# Delay (tRCD):
RAS# Precharge (tRP):
Precharge Delay (tRAS):
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance Level: AUTO
Read delay phase adjust: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 6
Ranks Read to Read (tRDRD): 6
Ranks Write to Read (tWRRD): 5
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

10/08/07 Bios template:


Adds a Read delay phase adjust option in DRAM timings menu.

Code:
CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio:
- Target CPU Clock:
CPU Clock:
Boot Up Clock:
DRAM Speed:
- Target DRAM Speed:
PCIE Clock: 100mhz

Voltage Settings
CPU VID Control:
CPU VID Special Add:
DRAM Voltage Control:
SB 1.05V Voltage:
SB Core/CPU PLL Voltage:
NB Core Voltage:
CPU VTT Voltage:
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: AUTO
- Enhance Addressing: AUTO
- Channel 1 CLK fine delay: AUTO
- Channel 2 CLK fine delay: AUTO

CAS Latency Time (tCL): 
RAS# to CAS# Delay (tRCD):
RAS# Precharge (tRP):
Precharge Delay (tRAS):
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance Level: AUTO
Read delay phase adjust: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 6
Ranks Read to Read (tRDRD): 6
Ranks Write to Read (tWRRD): 5
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

27/07/07 Bios template:


Use this template to share your DFI UT P35-T2R bios settings

Code:
CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio:
- Target CPU Clock:
CPU Clock:
Boot Up Clock:
DRAM Speed:
- Target DRAM Speed:
PCIE Clock: 100mhz

Voltage Settings
CPU VID Control:
CPU VID Special Add:
DRAM Voltage Control:
SB 1.05V Voltage:
SB Core/CPU PLL Voltage:
NB Core Voltage:
CPU VTT Voltage:
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: AUTO
- Enhance Addressing: AUTO
- Channel 1 CLK fine delay: AUTO
- Channel 2 CLK fine delay: AUTO

CAS Latency Time (tCL): 
RAS# to CAS# Delay (tRCD):
RAS# Precharge (tRP):
Precharge Delay (tRAS):
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance Level: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 6
Ranks Read to Read (tRDRD): 6
Ranks Write to Read (tWRRD): 5
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Last edited by eva2000; 06-03-2009 at 04:10 PM.
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Old 28-08-2007, 04:18 PM   #2
eva2000
Administrator
eva2000's PC Specs
 
Join Date: Jul 22 2004
Location: Brisbane, Australia
Posts: 22,988
twitter.com/i4memorycom Facebook Page livestream.com/i4memorycom
Blog Entries: 42
Re: DFI LP UT P35-T2R bios templates

Bios settings explained:

Explanation of some bios settings from windwithme at http://www.xtremesystems.org/forums/...d.php?t=154151 and from DFI.

Exist Setup Shutdown: Mode 1 versus Mode 2
  • Mode 1: when the system was boot-up, it will run a little “diagnose”.
  • If the CPU frequency doesn’t change too much, it will skip the “shutdown”
  • function and rewrite the clock generator directly.
  • Mode 2: no matter how little the clock or DRAM’s ratio has been changed, the system still “shutdown” and reboot by itself.

Clock VCO Divider: This function is use to fix the clock generator’s divider and “NB Strap” by its jumper. Then, system wouldn’t be reboot again because it presumed itself is
not in an overclock status. (this function needs to cooperate with particular jumper)

Boot-up clock: This function can help you out by setting a lower boot up clock as a buffer, when your FSB is tweaked too high in the beginning. The process will to be : system boot up with “Boot-up clock” first, after that it will change to your highest FSB.

PCIE Slot Config: PCIE2 / PCIE3 / PCIE4 slot speeds:
  • 1X 1X : PCIE 2 / 3 / 4 are running with 1X model
  • 4X NC: PCIE2 is running 4X mode, PCIE 3/4 will be disable and on board LAN1 will be disable as well.

GTL+ buffer Strength: It is adjustment option for North-Bridge reference voltage strength.

Host Slew Rate: It is adjustment option for North-Bridge voltage driving strength.

Enhance Data Transmitting: DFI specifically designed a “fine-tune mode” for DATA transmitting performance, Normal for lowest performance, Fast for highest performance, Default AUTO will automatically adjust performance based on current system Front Side BIOS.

Enhance Addressing: DFI specifically designed a “fine-tune mode” for DATA addressing, “Normal” for lowest performance, “Fast” for highest performance, Default AUTO will automatically adjust performance based on current system Front Side BIOS.

CLK fine delay: (there are channel 1,2 in current bios, it going to separate to be 4 items for DIMM1~DIMM4 in upcoming BIOS):
  • Giving an easy explanation, after the CPU, PCIE, DRAM locked the clock phase by “PLL phase locked loop”, we can utilize the DRAM DLL to adjust DRAM operating phase by tuning DRAM DATA output phase forward or backward to create a better match with current DATA operating phase.
  • The BIOS will automatically calculate a parameter after system boot up.( The latest update BIOS will show the current value of this parameter.)
  • The best tuning range for finding the best DATA operating phase will be 3 ranks before or after this current value.

Performance level: It is tRD of DRAM parameter

Read delay phase adjust: It is the fine-tune feature for tRD

MCH ODT Latency: DRAM ODT read/Write latency. Basically ODT is On Die Termination, it likes a variable resistor termination to protect DATA signal integrity from high frequency interference.
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