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Old 15-08-2007, 09:05 PM   #1
eva2000
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Cool DFI LANParty UT P35-T2R Preview photos & Bios Screenshots

DFI LANParty UT P35-T2R Preview photos
&
Bios Screenshots


DFI was so kind as to send me one of their latest motherboards, DFI LANParty UT P35-T2R (DDR2) motherboard. As always lets start with some motherboard photos and bios screenshots. I decided to use Scythe Infinity heatsink with modded mounting mechanism and a single Spire 120x25mm 96cfm 0.25A fan to start with. CPU in photo is Intel Core 2 Duo E6750 G0 ES.









Backside photos

Transpiper Heatsink



Looking at the Transpiper installation manual it makes it alot clearer... there's only one Transpiper heatsink included and it can either be installed within a case via Southbridge mounting OR installed over the cpu with the copper plate wedged in between the cpu heatsink base and cpu IHS heatspreader with the heatpipe extending out the case like pictured here (thanks MrRevhead for photo). I think most folks will install it on southbridge unless the cpu method results in significant cpu temp drops/better oc'ing potential.

You can see the Transpiper heatsink in action on cpu side from photos here and here.

Note: with cpu method, installation manual mentions NOT to use 4 peg mounting heatsinks as the copper plate which is sandwiched between cpu heatsink and cpu IHS heatspreader raises the height of the heatsink and those 4 peg mounting heatsinks may not work. The manual suggests cpu heatsinks with 4 retention bolt/screw threads instead - preferably ones with where the 4 retention bolt/screw threads pass through a LGA775 backplate coming up through the backside of the motherboard.

Downloads:
Updates: 19/09/08

9/19 official bios http://img.lanparty.tw/Upload/BIOS/CM/LP35D919.zip
Update Intel new micro code for support Intel Q9xxx CPUs.
Updates: 30/06/08

5/2 bios http://us.dfi.com.tw/Support/Downloa...FLAG=A&SITE=US
Major Reasons of Change:
The system can’t boot up in windows Vista 64bits when The motherboard with Intel Q9650 CPU and EIST function was disabled.
3/17 bios http://us.dfi.com.tw/Support/Downloa...FLAG=A&SITE=US
Major Reasons of Change:
Added warning message for over voltage.
2/14 bios http://us.dfi.com.tw/Support/Downloa...FLAG=A&SITE=US
Major Reasons of Change:
Added VTT Voltage control for Intel 45nm CPUs.
12/24 bios http://us.dfi.com.tw/Support/Downloa...FLAG=A&SITE=US
Major Reasons of Change:
1. Change ICH9R AHCI ROM.
2. Pach for QX9650(45nm CPU) radio issue .
3. Adjust dram tfine item value .
4. Add O.C fail item.
11/07 bios http://us.dfi.com.tw/Support/Downloa...FLAG=A&SITE=US
Major Reasons of Change:
Update Micro code for Yorkfield and Wolfdale.
Updates: 22/09/07

9/13 bios is officially out now http://us.dfi.com.tw/Support/Downloa...FLAG=A&SITE=US
Major Reasons of Change:
1.Enhance data transmitting added turbo.
2.Fixed cdrom name error in setup.
3.Added CMD Tfine control Tfine Item.
4.Added Tras 1~8.
5.Added T2 Dispatch item.
6.Change Read delay phase adjust item config.
Updates: 27/08/07

Just received 8/23 bios as well change log

http://fileshosts.com/intel/DFI/DFI_...a/LP35D823.zip

8/23 bios

1. "added ALC888 SSID.
2. Modifying "" CPU VID Special Add"" percentage table "
3. Fixed can't boot from sata cdrom when enable raid. We have change the ICH9 AHCI and RAID BIOS initial method to fix RAID building issue
Have yet to try it

Last edited by eva2000; 24-02-2009 at 09:57 PM.
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Old 15-08-2007, 09:17 PM   #2
eva2000
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Re: DFI LANParty UT P35-T2R Preview photos & Bios Screenshost

DFI LANParty UT P35-T2R shipped with the initial 27/07/07 bios. There's a 10/08/07 beta bios out now which I now have flashed to.

Here's the 27/07/07 bios screenshots:




























Last edited by eva2000; 16-08-2007 at 07:06 AM.
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Old 15-08-2007, 09:35 PM   #3
eva2000
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Re: DFI LANParty UT P35-T2R Preview photos & Bios Screenshost

19/09/08 Bios template:


Use this template to share your DFI UT P35-T2R bios settings

CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio:
CPU N/2 Ratio: Disabled
- Target CPU Clock:
CPU Clock:
Boot Up Clock:
DRAM Speed:
- Target DRAM Speed:
PCIE Clock: 100mhz

Voltage Settings
CPU VID Control:
CPU VID Special Add:
DRAM Voltage Control:
SB 1.05V Voltage:
SB Core/CPU PLL Voltage:
NB Core Voltage:
CPU VTT Voltage:
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: AUTO (Turbo needs high NB volts)
- Enhance Addressing: AUTO
- T2 Dispatch: Disabled (Disable for better memory stability)

Clock Setting Fine Delay
Tfine Item Value Degree: 70ps (10ps to 160ps range)

Ch1 Clock Crossing Setting: Aggressive for better performance, Relax for stability
- DIMM 1 CLK fine delay: Current
- DIMM 2 CLK fine delay: Current
- Ch 1 Command fine delay: Current
- Ch 1 Control fine delay: Curent

Ch2 Clock Crossing Setting: Aggressive for better performance, Relax for stability
- DIMM 3 CLK fine delay: Current
- DIMM 4 CLK fine delay: Current
- Ch 2 Command fine delay: Current
- Ch 2 Control fine delay: Curent

Ch1Ch2 CommonClock Setting: Auto

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)

CAS Latency Time (tCL):
RAS# to CAS# Delay (tRCD):
RAS# Precharge (tRP):
Precharge Delay (tRAS):
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter
- Channel 1 Phase 0 Pull-In: Auto (each Phase when enabled = (Common tRD - 1)
- Channel 1 Phase 1 Pull-In: Auto
- Channel 1 Phase 2 Pull-In: Auto
- Channel 1 Phase 3 Pull-In: Auto
- Channel 1 Phase 4 Pull-In: Auto

- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 6
Ranks Read to Read (tRDRD): 6
Ranks Write to Read (tWRRD): 5
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

13/09/07 Bios template:


9/13 bios download http://us.dfi.com.tw/Support/Downloa...FLAG=A&SITE=US

Code:
Major Reasons of Change:
1.Enhance data transmitting added turbo.
2.Fixed cdrom name error in setup.
3.Added CMD Tfine control Tfine Item.
4.Added Tras 1~8.
5.Added T2 Dispatch item.
6.Change Read delay phase adjust item config.
Code:
CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio:
- Target CPU Clock:
CPU Clock:
Boot Up Clock:
DRAM Speed:
- Target DRAM Speed:
PCIE Clock: 100mhz

Voltage Settings
CPU VID Control:
CPU VID Special Add:
DRAM Voltage Control:
SB 1.05V Voltage:
SB Core/CPU PLL Voltage:
NB Core Voltage:
CPU VTT Voltage:
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: AUTO (Turbo needs high NB volts)
- Enhance Addressing: AUTO
- T2 Dispatch: Disabled (Disable for better memory stability)

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: Aggressive for better performance, Relax for stability
- DIMM 1 CLK fine delay: Current (increasing delay by 1 or 2 & decrease Command/Control delay by 1 or 2 may help 1T/2T oc'ing)
- DIMM 2 CLK fine delay: Current
- Ch 1 Command fine delay: Current
- Ch 1 Control fine delay: Curent

Ch2 Clock Crossing Setting: Aggressive for better performance, Relax for stability
- DIMM 3 CLK fine delay: Current (increasing delay by 1 or 2 & decrease Command/Control delay by 1 or 2 may help 1T/2T oc'ing)
- DIMM 4 CLK fine delay: Current
- Ch 2 Command fine delay: Current
- Ch 2 Control fine delay: Curent

Ch1Ch2 CommonClock Setting: Auto

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)

CAS Latency Time (tCL): 
RAS# to CAS# Delay (tRCD):
RAS# Precharge (tRP):
Precharge Delay (tRAS):
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter
- Channel 1 Phase 0 Pull-In: Auto (each Phase when enabled = (Common tRD - 1)
- Channel 1 Phase 1 Pull-In: Auto
- Channel 1 Phase 2 Pull-In: Auto
- Channel 1 Phase 3 Pull-In: Auto
- Channel 1 Phase 4 Pull-In: Auto

- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled
23/08/07 Bios template:


8/23 bios download http://us.dfi.com.tw/Support/Downloa...FLAG=A&SITE=US

Change log:
Code:
Major Reasons of Change:
1. Added LAN, Audio,1394, IDE chip Item.
2. Support DDR2 533 Module when NB strap jump set to 333MHz.
3. Fixed can't install vista when plus 4GB memory.
4. Fixed Vista64 DRAM size issue.
5. Fixed EIST can't be disabled in vista.
6. Fixed can't boot from SATA CD-ROM when Enable RAID mode..
Use this template to share your DFI UT P35-T2R bios settings

Code:
CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio:
- Target CPU Clock:
CPU Clock:
Boot Up Clock:
DRAM Speed:
- Target DRAM Speed:
PCIE Clock: 100mhz

Voltage Settings
CPU VID Control:
CPU VID Special Add:
DRAM Voltage Control:
SB 1.05V Voltage:
SB Core/CPU PLL Voltage:
NB Core Voltage:
CPU VTT Voltage:
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: AUTO
- Enhance Addressing: AUTO
- DIMM 1 CLK fine delay: Current
- DIMM 2 CLK fine delay: Current
- DIMM 3 CLK fine delay: Current
- DIMM 4 CLK fine delay: Current

CAS Latency Time (tCL): 
RAS# to CAS# Delay (tRCD):
RAS# Precharge (tRP):
Precharge Delay (tRAS):
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance Level: AUTO
Read delay phase adjust: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 6
Ranks Read to Read (tRDRD): 6
Ranks Write to Read (tWRRD): 5
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

10/08/07 Bios template:


Adds a Read delay phase adjust option in DRAM timings menu.

Code:
CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio:
- Target CPU Clock:
CPU Clock:
Boot Up Clock:
DRAM Speed:
- Target DRAM Speed:
PCIE Clock: 100mhz

Voltage Settings
CPU VID Control:
CPU VID Special Add:
DRAM Voltage Control:
SB 1.05V Voltage:
SB Core/CPU PLL Voltage:
NB Core Voltage:
CPU VTT Voltage:
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: AUTO
- Enhance Addressing: AUTO
- Channel 1 CLK fine delay: AUTO
- Channel 2 CLK fine delay: AUTO

CAS Latency Time (tCL): 
RAS# to CAS# Delay (tRCD):
RAS# Precharge (tRP):
Precharge Delay (tRAS):
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance Level: AUTO
Read delay phase adjust: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 6
Ranks Read to Read (tRDRD): 6
Ranks Write to Read (tWRRD): 5
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

27/07/07 Bios template:


Use this template to share your DFI UT P35-T2R bios settings

Code:
CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio:
- Target CPU Clock:
CPU Clock:
Boot Up Clock:
DRAM Speed:
- Target DRAM Speed:
PCIE Clock: 100mhz

Voltage Settings
CPU VID Control:
CPU VID Special Add:
DRAM Voltage Control:
SB 1.05V Voltage:
SB Core/CPU PLL Voltage:
NB Core Voltage:
CPU VTT Voltage:
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: AUTO
- Enhance Addressing: AUTO
- Channel 1 CLK fine delay: AUTO
- Channel 2 CLK fine delay: AUTO

CAS Latency Time (tCL): 
RAS# to CAS# Delay (tRCD):
RAS# Precharge (tRP):
Precharge Delay (tRAS):
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance Level: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 6
Ranks Read to Read (tRDRD): 6
Ranks Write to Read (tWRRD): 5
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Bios settings explained:

Explanation of some bios settings from windwithme at http://www.xtremesystems.org/forums/...d.php?t=154151 and from DFI.

Exist Setup Shutdown: Mode 1 versus Mode 2
  • Mode 1: when the system was boot-up, it will run a little “diagnose”. If the CPU frequency doesn’t change too much, it will skip the “shutdown” function and rewrite the clock generator directly.
  • Mode 2: no matter how little the clock or DRAM’s ratio has been changed, the system still “shutdown” and reboot by itself.

Clock VCO Divider: This function is use to fix the clock generator’s divider and “NB Strap” by its jumper. Then, system wouldn’t be reboot again because it presumed itself is
not in an overclock status. (this function needs to cooperate with particular jumper)

Boot-up clock: This function can help you out by setting a lower boot up clock as a buffer, when your FSB is tweaked too high in the beginning. The process will to be : system boot up with “Boot-up clock” first, after that it will change to your highest FSB.

PCIE Slot Config: PCIE2 / PCIE3 / PCIE4 slot speeds:
  • 1X 1X : PCIE 2 / 3 / 4 are running with 1X model
  • 4X NC: PCIE2 is running 4X mode, PCIE 3/4 will be disable and on board LAN1 will be disable as well.

GTL+ buffer Strength: It is adjustment option for North-Bridge reference voltage strength.

Host Slew Rate: It is adjustment option for North-Bridge voltage driving strength.

Enhance Data Transmitting: DFI specifically designed a “fine-tune mode” for DATA transmitting performance, Normal for lowest performance, Fast for highest performance, Default AUTO will automatically adjust performance based on current system Front Side BIOS.

Enhance Addressing: DFI specifically designed a “fine-tune mode” for DATA addressing, “Normal” for lowest performance, “Fast” for highest performance, Default AUTO will automatically adjust performance based on current system Front Side BIOS.

CLK fine delay: (there are channel 1,2 in current bios, it going to separate to be 4 items for DIMM1~DIMM4 in upcoming BIOS):
  • Giving an easy explanation, after the CPU, PCIE, DRAM locked the clock phase by “PLL phase locked loop”, we can utilize the DRAM DLL to adjust DRAM operating phase by tuning DRAM DATA output phase forward or backward to create a better match with current DATA operating phase.
  • The BIOS will automatically calculate a parameter after system boot up.( The latest update BIOS will show the current value of this parameter.)
  • The best tuning range for finding the best DATA operating phase will be 3 ranks before or after this current value.

Performance level: It is tRD of DRAM parameter

Read delay phase adjust: It is the fine-tune feature for tRD

MCH ODT Latency: DRAM ODT read/Write latency. Basically ODT is On Die Termination, it likes a variable resistor termination to protect DATA signal integrity from high frequency interference.

Last edited by eva2000; 06-03-2009 at 05:09 PM.
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Old 15-08-2007, 09:36 PM   #4
eva2000
Administrator
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Join Date: Jul 22 2004
Location: Brisbane, Australia
Posts: 23,021
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Blog Entries: 42
Re: DFI LANParty UT P35-T2R Preview photos & Bios Screenshost

Looks like coretemp and Smartguardian both reporting abnormally low cpu temps - way below chipset/PWM temps at idle.

System
  • Intel Core 2 Duo E6750 ES - L710A438 G0
  • Scythe Infinity with modded mount + 120x25mm Spire 96cfm fan
  • Transpiper heatsink NOT installed
  • DFI LP UT P35-T2R 8/10 bios flashed from 7/27
  • 128MB Gainward FX5200 PCI
  • 2GB Corsair 10000C5D Dominator on Green dimm slots
  • 80GB Hitachi 7K80 SATA
  • LiteON CD-RW
  • 700W OCZ GameXStream
  • WinXP Pro SP2

Idle


Load


With default AUTO subtimings, Memset and Everest report the subtiming values as:



Bios Settings Used:
CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 8x
- Target CPU Clock: 2664Mhz
CPU Clock: 333FSB
Boot Up Clock: AUTO
DRAM Speed: 333MHZ/667MHZ
- Target DRAM Speed: DDR2-667Mhz
PCIE Clock: 100Mhz

Voltage Settings
CPU VID Control: 1.325 (1.34v bios / SG 1.32v idle/load)
CPU VID Special Add: AUTO
DRAM Voltage Control: 1.80v (1.77v bios /SG 1.72v idle)
SB 1.05V Voltage: 1.07v
SB Core/CPU PLL Voltage: 1.55v
NB Core Voltage: 1.33v
CPU VTT Voltage: 1.20v
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: AUTO
- Enhance Addressing: AUTO
- Channel 1 CLK fine delay: Current[13]
- Channel 2 CLK fine delay: Current[11]

CAS Latency Time (tCL): 4
RAS# to CAS# Delay (tRCD): 4
RAS# Precharge (tRP): 4
Precharge Delay (tRAS): 12
All Precharge to Act: AUTO (4)
REF to ACT Delay (tRFC): AUTO (42)
Performance Level: AUTO (7)
Read delay phase adjust: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO (13)
Rank Write to Read (tWTR): AUTO (10)
ACT to ACT Delay (tRRD): AUTO (3)
Read to Write Delay (tRDWR): AUTO (8)
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO (3)
ALL PRE to Refresh: AUTO (4)

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Last edited by eva2000; 16-08-2007 at 10:11 AM.
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Old 15-08-2007, 09:36 PM   #5
eva2000
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Join Date: Jul 22 2004
Location: Brisbane, Australia
Posts: 23,021
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Blog Entries: 42
Re: DFI LANParty UT P35-T2R Preview photos & Bios Screenshost

E6750 @8x450FSB 1:1


Next stop is my sweet spot @3600Mhz. Again coretemp/SG temps are grossly underreported. I suspect by as much as 15C under reported ?

Idle:


Load:


Bios Settings Used:
CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 8x
- Target CPU Clock: 3600Mhz
CPU Clock: 450FSB
Boot Up Clock: AUTO
DRAM Speed: 333MHZ/667MHZ
- Target DRAM Speed: DDR2-901Mhz
PCIE Clock: 100Mhz

Voltage Settings
CPU VID Control: 1.4625 (1.48v bios / SG 1.48v idle, 1.45v load)
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.05v (2.01v bios /SG 1.98v idle/load)
SB 1.05V Voltage: 1.07v
SB Core/CPU PLL Voltage: 1.55v
NB Core Voltage: 1.33v
CPU VTT Voltage: 1.20v
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: AUTO
- Enhance Addressing: AUTO
- Channel 1 CLK fine delay: Current[13]
- Channel 2 CLK fine delay: Current[11]

CAS Latency Time (tCL): 4
RAS# to CAS# Delay (tRCD): 4
RAS# Precharge (tRP): 4
Precharge Delay (tRAS): 12
All Precharge to Act: AUTO (4)
REF to ACT Delay (tRFC): AUTO (42)
Performance Level: AUTO (7)
Read delay phase adjust: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO (13)
Rank Write to Read (tWTR): AUTO (10)
ACT to ACT Delay (tRRD): AUTO (3)
Read to Write Delay (tRDWR): AUTO (8)
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO (3)
ALL PRE to Refresh: AUTO (4)

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Last edited by eva2000; 16-08-2007 at 08:58 PM.
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Old 15-08-2007, 09:36 PM   #6
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Re: DFI LANParty UT P35-T2R Preview photos & Bios Screenshost

Super Pi 32M compare @8x450FSB 1:1


Time to figure out all these subtimings at 1:1 divider first. I'll update with more comparison results as I go. Right now plan to compare the following
  • 450mhz 4-4-4-12 All subtimings set to AUTO
  • 450mhz 4-4-4-12 Most subtimings manually set
  • 450mhz 4-4-4-12 Most subtimings manually set and play with Enhanced Data transmitting option = FAST
  • 450mhz 4-4-4-12 Most subtimings manually set and play with Enhanced Addressing option = FAST
  • 450mhz 4-4-4-12 Most subtimings manually set and play with both Enhanced Data transmitting + Enhanced Addressing option both set to FAST
  • 450mhz 4-4-4-9* Most subtimings manually set and play with both Enhanced Data transmitting + Enhanced Addressing option both set to FAST
* tRAS of 9 is lowest selectable option in 8/10 bios

Bios Settings Used:
CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 8x
- Target CPU Clock: 3600Mhz
CPU Clock: 450FSB
Boot Up Clock: AUTO
DRAM Speed: 333MHZ/667MHZ
- Target DRAM Speed: DDR2-901Mhz
PCIE Clock: 100Mhz

Voltage Settings
CPU VID Control: 1.4625 (1.48v bios / SG 1.48v idle, 1.45v load)
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.05v and 2.10v
SB 1.05V Voltage: 1.07v
SB Core/CPU PLL Voltage: 1.55v
NB Core Voltage: 1.33v and 1.45
CPU VTT Voltage: 1.20v
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: AUTO
- Enhance Addressing: AUTO
- Channel 1 CLK fine delay: Current[0]
- Channel 2 CLK fine delay: Current[14]

CAS Latency Time (tCL): 4
RAS# to CAS# Delay (tRCD): 4
RAS# Precharge (tRP): 4
Precharge Delay (tRAS): 12 vs 12 vs 9 (lowest available in bios = 9)
All Precharge to Act: AUTO (4) vs 4
REF to ACT Delay (tRFC): AUTO (42) vs 30
Performance Level: AUTO (7) vs 7
Read delay phase adjust: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO (13) vs 11
Rank Write to Read (tWTR): AUTO (10) vs 10
ACT to ACT Delay (tRRD): AUTO (3) vs 3
Read to Write Delay (tRDWR): AUTO (8) vs 8
Ranks Write to Write (tWRWR): AUTO vs 8
Ranks Read to Read (tRDRD): AUTO vs 6
Ranks Write to Read (tWRRD): AUTO vs 5
Read CAS# Precharge (tRTP): AUTO (3) vs 3
ALL PRE to Refresh: AUTO (4) vs 4

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled
Notes:
  • With current memory 2GB Corsair 10000C5D Dominators, the tWR is pretty sensitive when it comes to values below 11. tWR of 10 in bios resulted in memtest86+ v1.70 test #5 errors almost immediately at the voltages tested at 2.15v vdimm and 1.45v NB and not until NB volt of 1.65v did number of errors reduce to around 6 errors after 4th pass of a memtest test #5 loop. Haven't figured out what voltages or settings make tWR of 10 stable for memtest yet so stick with tWR of 11 from bios.
  • Once loaded into windows using memset, you can now see why tWR was so sensitive. tWR set in bios of 11 in fact reports in memset ast tWR of 10. So no wonder why tWR of 10 in bios errored out as it probably resulted in memset reported value for tWR below 10. Same goes for tWTR in bios set at 10 resulted in memset reporting tWTR of 9. This is similar to Asus P5K series where what is set in bios for tWR and tWTR don't reflect with what memset in windows reports as you will see below
  • Weird lowest tRAS value available in DFI LP UT P35-T2R 8/10 bios is 9 ??? I hope DFI will be fixing this in later bioses - since we already know DFI will have a bios to split the current 2 Channel CLK fine delay options into 4 separate options for each memory dimm slot
  • Seems what is the most accurate indicator of Super Pi 32M performance is Everest Read bandwidth and maybe Everest Latency.





Subtimings = ALL AUTO with 2.05v vdimm bios set

Super Pi 32M = 13min 49.984s
Everest Read = 8767
Everest Write = 8229
Everest Copy = 8112
Everest Latency = 56.2ns
Sandra XI SP2 Buffered = 7960 / 7999
Sandra XI SP2 Unbuffered = 5222 / 5288

Subtimings = Nearly all manually set as per above listed subtimings with 2.10v vdimm bios set

Super Pi 32M = 13min 46.031s
Everest Read = 8842
Everest Write = 8219
Everest Copy = 8250
Everest Latency = 55.7ns
Sandra XI SP2 Buffered = 8022 / 8057
Sandra XI SP2 Unbuffered = 5311 / 5385

Subtimings = Nearly all manually set as per above listed subtimings with 2.10v vdimm bios set
+
Enhance Data Transmitting = FAST


Super Pi 32M = 13min 45.141s
Everest Read = 8840
Everest Write = 8220
Everest Copy = 8235
Everest Latency = 55.8ns
Sandra XI SP2 Buffered = 8019 / 8053
Sandra XI SP2 Unbuffered = 5246 / 5311

Subtimings = Nearly all manually set as per above listed subtimings with 2.10v vdimm bios set
+
Enhance Addressing = FAST


Super Pi 32M = 13min 41.062s
Everest Read = 9042
Everest Write = 8221
Everest Copy = 8367
Everest Latency = 53.7ns
Sandra XI SP2 Buffered = 8125 / 8161
Sandra XI SP2 Unbuffered = 5380 / 5464

Subtimings = Nearly all manually set as per above listed subtimings with 2.10v vdimm bios set
+
Enhance Data Transmitting = FAST
+
Enhance Addressing = FAST


Super Pi 32M = 13min 39.219s
Everest Read = 9048
Everest Write = 8220
Everest Copy = 8352
Everest Latency = 53.6ns
Sandra XI SP2 Buffered = 8106 / 8155
Sandra XI SP2 Unbuffered = 5329 / 5391

4-4-4-9 with Subtimings = Nearly all manually set as per above listed subtimings with 2.10v vdimm bios set
+
Enhance Data Transmitting = FAST
+
Enhance Addressing = FAST


Super Pi 32M = 13min 38.203s
Everest Read = 9055
Everest Write = 8218
Everest Copy = 8329
Everest Latency = 53.6ns
Sandra XI SP2 Buffered = 8106 / 8139
Sandra XI SP2 Unbuffered = 5388 / 5451

Compared with E6750 G0 ES on Asus Blitz Formula with 2GB Crucial Ballistix Tracer PC2-8500 @8x450FSB 1:1 4-4-4-5 3-30-3-3-3:

Super Pi 32M = 13min 35.828s
Everest Read = 8996
Everest Write = 8215
Everest Copy = 8297
Everest Latency = 53.4ns

Memset reported subtimings compared


Let's compare the memset reported subtiming values for fastest 32M on DFI LP UT P35-T2R and Asus Blitz Formula

DFI LP UT P35-T2R = 4-4-4-9 4-30-7-10-9-3-8-3-4-2
Asus Blitz Formula = 4-4-4-5 4-30-7-10-10-3-8-3-4-2

It seems performance is pretty close, with DFI LP UT P35-T2R with tRAS of 5 probably could shave another few seconds off Super Pi 32M time to hit Asus Blitz Formula's time. Yes, I could set tRAS to 5 in memset for DFI board, but I wanted to see what kind of performance there is from straight bios set to windows boot

Last edited by eva2000; 17-08-2007 at 05:04 PM.
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Old 15-08-2007, 09:36 PM   #7
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Re: DFI LANParty UT P35-T2R Preview photos & Bios Screenshost

DFI LP UT P35-T2R: Max FSB E6750 G0 ES


Next is looking at MAX FSB. My E6750 on Asus P5K Deluxe maxed out at 495-500FSB with CPU PLL 1.8v voltage. I suspect this is a cpu FSB wall as it's pretty much the same on DFI LP UT P35-T2R maxing out FSB around 495-500FSB but needing CPU PLL 1.95v since next option below it was 1.75v with clockgen voltage at 3.75v. I could boot into memtest86+ v1.70 at 506FSB but it would hang in test #7 (which might be a good test for max FSB for cpus ? ).

System
  • Intel Core 2 Duo E6750 ES - L710A438 G0
  • Scythe Infinity with modded mount + 120x25mm Spire 96cfm fan
  • Transpiper heatsink NOT installed
  • DFI LP UT P35-T2R 8/10 bios flashed from 7/27
  • 128MB Gainward FX5200 PCI
  • 2GB Crucial Ballistix Tracer PC2-8500 naked modules Green dimm slots
  • 80GB Hitachi 7K80 SATA
  • LiteON CD-RW
  • 700W OCZ GameXStream
  • WinXP Pro SP2

7x500FSB 1:1


Single Super Pi 32M needed 2.19v bios set vdimm but dual Super Pi 32M needed 2.27v vdimm



Half way mark for dual 32M


Dual Super Pi 32M complete


Everest Bandwidth & Cinebench R10


Winrar v3.70 Trial


Bios Settings Used:
CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 7x
- Target CPU Clock: 3500Mhz
CPU Clock: 500FSB
Boot Up Clock: AUTO
DRAM Speed: 333MHZ/667MHZ
- Target DRAM Speed: DDR2-1001Mhz
PCIE Clock: 100Mhz

Voltage Settings
CPU VID Control: 1.4625v
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.19v
SB 1.05V Voltage: 1.15v
SB Core/CPU PLL Voltage: 1.95v
NB Core Voltage: 1.50v
CPU VTT Voltage: 1.40v
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.75v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: FAST
- Enhance Addressing: FAST
- Channel 1 CLK fine delay: 14
- Channel 2 CLK fine delay: 14

(values in brackets next to AUTO is what memset sees)
CAS Latency Time (tCL): 4
RAS# to CAS# Delay (tRCD): 4
RAS# Precharge (tRP): 4
Precharge Delay (tRAS): 9
All Precharge to Act: 4
REF to ACT Delay (tRFC): 30
Performance Level: 7
Read delay phase adjust: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): 11
Rank Write to Read (tWTR): 11
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): 3
ALL PRE to Refresh: AUTO 4

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled
7x500FSB 5:6 divider


Notes:
  • With 5:6 didvider tWR and tWTR actually show same values in memset as what's set in bios which differs from 1:1 divider where tWR and tWTR show 1 value below in memset compared to what is set in bios.

Single Super Pi 1M & 32M





Half way mark for dual 32M


Dual Super Pi 32M complete


Everest Bandwidth & Cinebench R10


Winrar v3.70 Trial


Without other cpuz/memset/SG windows open a bit higher




Bios Settings Used:
CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 7x
- Target CPU Clock: 3500Mhz
CPU Clock: 500FSB
Boot Up Clock: AUTO
DRAM Speed: 266MHZ/667MHZ
- Target DRAM Speed: DDR2-1201Mhz
PCIE Clock: 100Mhz

Voltage Settings
CPU VID Control: 1.4375v
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.27v
SB 1.05V Voltage: 1.15v
SB Core/CPU PLL Voltage: 1.95v
NB Core Voltage: 1.53v
CPU VTT Voltage: 1.40v
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.75v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: FAST
- Enhance Addressing: FAST
- Channel 1 CLK fine delay: 14
- Channel 2 CLK fine delay: 14

(values in brackets next to AUTO is what memset sees)
CAS Latency Time (tCL): 5
RAS# to CAS# Delay (tRCD): 5
RAS# Precharge (tRP): 4
Precharge Delay (tRAS): 9
All Precharge to Act: 4
REF to ACT Delay (tRFC): 30
Performance Level: 7
Read delay phase adjust: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): 11
Rank Write to Read (tWTR): 11
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): 3
ALL PRE to Refresh: AUTO 4

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Last edited by eva2000; 20-08-2007 at 01:49 AM.
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Old 15-08-2007, 09:36 PM   #8
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Re: DFI LANParty UT P35-T2R Preview photos & Bios Screenshost

Folks have asked how does this DFI board compare to Asus P35 chipset boards. So here's my initial findings as at August 21, 2007.

Only done very preliminary tests on DFI LP UT P35-T2R (which I only setup on Aug 15, 2007) compared to Asus P5K Deluxe/P5K3 Deluxe and Blitz Formula/Blitz Extreme which I have had since May and July, 2007 respectively. Also DFI LP UT P35-T2R bios is still undergoing alot of improvements while Asus has had a head start on bios maturity on their P5K and Blitz series.

-------------------------------------------------------------------------
DFI LP UT P35-T2R
Pros:
  • Slightly more stable oc at borderline max FSB - difference not more than 1-5FSB though.
  • PWM temps are pretty decent around 33-36C in 22-25C room temps but open desktop bench setup (no case) and using E6750 G0 ES dual core. But Smartguardian under reports cpu temps by 15-16C so not sure about the PWM reported temps. Feels cool to touch heatsinks though.
  • Much easier bios display of target cpu and memory clocks - see bios screenshot here. Instead of taking out a calculator and needing to sometimes work out your end result cpu and mem clocks on dividers and cpu multipliers, the DFI P35 bios shows the target cpu and mem clocks on the fly as you adjust your FSB/Mem clocks via dividers.
  • Exit setup shutdown bios option - basically has 2 modes - one to act like all P35 chipsets whenever divider or strap changes it will do the auto shutdown and boot up routine. The other mode allows you to skip that shutdown for minor changes only so less shutdowns. Such a mode is good for after you have figured out your stable settings.
  • Vcore droop control - eliminates vcore droop under load which is same function Asus P5K Deluxe/P5K3 Deluxe and Blitz Formula/Blitz Extreme have.
  • Alot of additional bios settings which Asus P35 motherboards don't have which can potentially squeeze out more cpu/fsb/memory overclocks. GTL+ ref volt and clockgen voltage and CLK fine delay etc options. But you need to spend considerable time to figure these out for moving beyond your initial barriers - meaning you should be able to max out your cpu/fsb/memory clocks without tuning these options much at all. But tuning them might squeeze out more stability and/or headroom.
  • Bios chip is replaceable so you can hot flash or grab another bios chip if you mess up your bios flash updates.
  • Very clean cpu socket area. Great for water cooling and extreme sub zero cooling enthusiasts (insulating the motherboard will be much easier)
  • Both PS/2 keyboard/mouse ports available. Asus P35 boards removed the PS/2 mouse port - folks with KVM PS/2 based switches would need to buy a completely new USB based KVM switch or use a separate USB mouse from your PS/2 KVM switch attached PS/2 mouse.
  • With double slot heatsink based video cards in crossfire mode, you potentially have 2 available PCI slots free versus Asus P35 series with 1 available PCI slot (but depends on how thick your PCI device is)
  • Ez Clear feature, to clear cmos no jumper switching is needed (you can if you want). Instead hit the reset button and hold it and then hit the power button holding them both for 4 seconds. Then release power button followed by reset button. This procedure will clear cmos for you


Cons:
  • Poor failed overclock recovery - nearly always need a clear cmos. Sometimes hitting reset on a bad oc or frozen screen initiates a clear cmos on reboot. [Update: 30/08/07 - if on power down, you hit HOME key on keyboard while powering up, instead of clearing cmos totally, you can just reset the FSB to default keeping other bios settings intact]
  • Lowest selectable tRAS value is only 9.. can't select below 9 ? Bios update fix probably. Update: 24/09/07 - fixed in 9/13 official bios
  • Not much bios monitoring options available and still using Smartguardian which is very inaccurate i.e vdimm set at 2.45v = 2.43v idle in SG and 2.39-2.41v under load in SG. No idea of real voltages as I don't know the DMM reading points on the motherboard. Same goes for vcore, NB, VTT they're slightly off from what is set in bios.
  • Inaccurate vcore settings when VID + VID Special in use no where near what the calculated value should be. Example, 1.6v + 5.9% should = 1.694v but real value is 1.63v. 1.6v + 6-10% = 1.696-1.76v but real value = 1.64-1.68v. Some of the lower VID + VID Special values are more undervolted that these.
  • Having issues oc'ing Micron D9GMH/GKX based memory with 5-5-5-15 timings such as Corsair 10000C5D Dominators and Crucial Ballistix Tracer PC2-8500 on 1:2 and 5:8 dividers (no system boot with E6750 @8x333FSB), very limited oc'ing headroom on 2:3 divider (10000C5D ~589mhz 5-5-5-15 and Crucial PC2-8500 ~600mhz 5-5-5-15 regardless of volts used). This same Crucial memory on Asus P5K Deluxe can do 625mhz 5-5-5-15 at 2.1v on 2:3 divider and 651mhz 5-5-5-15 at 2.45v max. Strangely, same Crucial memory in 4-4-4-9 in 2:3 has no problems hitting 576mhz 4-4-4-9 at 2.45v bios set which is 6mhz higher than Asus P5K Deluxe.
  • So you can say, DFI P35 has slightly better 4-4-4-9 overclocking but no where near as good 5-5-5-15 overclocking. Could be divider related, bios bugs or just the limited time I've spent playing with timings/subtimings and settings on DFI P35.
  • CLK fine delay settings in bios related to tweaking memory performance more. Still undergoing improvements with future bios updates right now. See bios screenshot here from 7/27 initial bios has 2 values and AUTO, in 8/10 beta bios now has 15 values 0-15, a current value and AUTO. Setting to current value will probably be the best way to start off and should be okay for most mild overclocks to start with. In future bioses (8/23 onwards), this option will be further split into 4 individual memory banks so you can tune each memory bank individually. Tricky to figure out optimal values as it depends on each individual memory module/PCB in each individual memory bank. Update: 24/09/07 - much improved in 8/23 and 9/13 official bios
    • Giving an easy explanation, after the CPU, PCIE, DRAM locked the clock phase by “PLL phase locked loop”, we can utilize the DRAM DLL to adjust DRAM operating phase by tuning DRAM DATA output phase forward or backward to create a better match with current DATA operating phase.
    • The BIOS will automatically calculate a parameter after system boot up.( The latest update BIOS will show the current value of this parameter.)
    • The best tuning range for finding the best DATA operating phase will be 3 ranks before or after this current value.
-------------------------------------------------------------------------
Asus P35 chipset series (Asus P5K Deluxe/P5K3 Deluxe and Blitz Formula/Blitz Extreme)
Pros:
  • Love bios Ez Flash2 feature, you can boot into bios to flash update your bios without a floppy by using USB drive or a FAT32 partitioned area on your hdds
  • Bios OC profile feature, save your oc'd settings and config to a FAT32 partitioned area on your hdd so you can restore from it to play with other known stable settings you figure out.
  • Solid and very good failed overclock recovery, since May/July 2007 with all my cpu and memory testing, I have probably only cleared cmos 4 - 6 times and majority of those times was when i first got the motherboards and didn't realise the fact that for failed overclocks all I need to do is hit reset button and it will come back up
  • Very clean cpu socket area. Great for water cooling and extreme sub zero cooling enthusiasts (insulating the motherboard will be much easier)
  • Blitz only series have 2 phase DDR2/DDR3 instead of 1 phase on P5K and other P35 series boards, which should allow more stable memory overclocking with 2 phase.
  • Blitz only series has crosslinx chip to provide x8 + x8 crossfire instead of x16 + x4 crossfire on all other P35 boards.
  • More accurate Asus PC Probe2 windows voltages from what is set in bios with exception of NB/VFSB and for P5K series vdimm.
  • Blitz series way better bios and PC Probe2 monitoring options with display for NB/VFSB/SB/CPU PLL and other voltages in windows
  • More accurate and easier to dial in vcore instead of messing with DFI P35's method of VID + VID Special percentages
  • Much higher and easier to achive 5-5-5-15 memory overclocking with solid 4-4-4-x overclocking only slightly behind DFI P35.
  • Probably easier to setup and get to a decent overclock than the current DFI P35 bios.

Cons:
  • Bios chip is soldered onboard, so bad bios flash means you need to RMA the entire motherboard I've used the USB flash drive/Ez Flash 2 in bios method of flashing my boards numerous times with no problems though.
  • P5K Deluxe/P5K3 Deluxe less max available vcore than DFI P35 board around 1.70v while Blitz series has close to 2.0v vcore.
  • No GTL+ Reference voltage tuning options like DFI P35 to potentially squeeze our more max FSB on your dual and quad core cpus. Although, current both Asus P35 and DFI P35 maxed out my E6750 GO ES at same 500FSB anyway. Could be because I have had limited time tuning GTL+ ref volts on DFI P35 though.
  • Potentially, some board layout issues with placement of IDE slot on P5K series and if double slot heatsink video cards are used - leaving 1 available PCI slot. The IDE placement on Blitz series is much better than P5K series.
  • Some folks have had raid issues or SATA disk detection issues.. I haven't had any of these problems though.
  • Blitz series only, crosslink chip while gives x8 + x8 crossfire has a potential future compatibility problem with PCIE 2.0 based graphics cards whereas regular P35 motherboards such as Asus P5K series or DFI P35 will not have that problem. No idea if there's a fix for this though.
  • Clear cmos jumper location on P5K series might be in a bad location where if you have double slot heatsink installed in PCI-E slot 1, it can block access to clear cmos jumper, so you need to remove video card before you can access clear cmos jumper. But the boards are solid for failed overclock recovery and have rarely needed using a clear cmos process
-------------------------------------------------------------------------

Last edited by eva2000; 25-09-2007 at 07:31 AM.
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