Join Date: Apr 29 2005
AMD Describes Road to 45-nm Processors
n academic papers presented this week, AMD will present its strategy toward catching up with Intel at the 45-nm node – a delicate balancing act that introduces several new manufacturing techniques.
AMD's 45-nm strategy is based on three fundamental techniques, AMD and IBM executives said Monday night: the use of immersion lithography, which uses a lens of purified water to help manufacture the components; an "ultra" low-k dielectric, which lowers the capacitance of the chip, allowing lower power consumption; and an improved version of "strained silicon," which has applied four different "stressers" to recoup some of the benefits lost through the process shrink, executives said.
AMD manufacturing executives said they're optimistic that the tools to build the new 45-nm microprocessors due in about eighteen months won't be significantly more expensive to manufacture than their predecessors. At this point, it's impossible to say what a 45-nm microprocessor will cost to manufacture versus a 65-nm version.
However, the cost of at least the immersion lithography tools "does not immediately appear different" than the previous cost of a new tool, said Nick Kepler, the vice president of logic technology development for AMD. He did not comment on the overall cost of manufacturing a chip on the 45-nm process, however.
IBM, AMD's logic development partner, will also present papers at the International Electron Device Meeting in San Francisco this week; AMD and IBM have a joint partnership to develop logic through 2011, although the agreement has only been formalized through the 45-nm manufacturing generation, and rests in part on approval by IBM's board to purchase the necessary capital equipment by Dec. 31, 2008.
The new 45-nm lines will be installed both in IBM's fabs in East Fishkill, N.Y., as well as at AMD's fabs in Dresden, Germany, and produced on a larger 300-mm wafer line.
Within the microprocessor space, competition is fought on several fronts. For years, designers attempted to improve the processor's clock rate, once the key selling attribute of a Pentium or AMD K6. By shifting a microprocessor's manufacturing line onto a finer manufacturing technology, the components can either be run at faster speeds at the same power consumption, or run at the same speed at lower power. Lately, the latter attribute's significance has increased, as PCs and servers have become "good enough" for many everyday tasks. Designers, too, are emphasizing efficiency.
AMD is also chasing Intel, which has currently has not only designed but began to sample its very first "Penryn" 45-nm processors. To catch up with Intel, AMD and IBM have outlined an 18-month goal to enter production. Intel also uses its own applications of immersion lithography and strained silicon. Foundry TSMC has also aggressively outlined plans to enter the current 65-nm generation, allowing fabless companies like Nvidia to keep up.
Historically, entering a new process generation has been risky, with both AMD and Intel stumbling at various points. However, executives said that the shared development between both AMD and IBM helps mitigate any possibility for errors.
"We have two fabs in a strong position to share info across the two sites in real time," said John Pellerin, director of logic technology development at AMD and the onsite project leader with IBM. "At Dresden, we can pull in the technologies quite early in time, nd start exercising as soon as possible the benefit there. You do have two fabs working in parallel, which helps mitigate the risk that you've mentioned."
Those types of manufacturing problems "are very much in the distant past," Kepler said.
The most novel aspect of the new techniques will be the use of immersion lithography, which shines the etching laser through a lens of purified water. Air is now an insufficient medium for lithography, as the wavelength of the light used is actually larger than the dimensions of the etched features. By beaming the laser through water, the light is bent slightly, which has the property of shrinking the effective wavelength down to a useable size.
According to Paul Agnello, the 45-nm project manager at IBM, the company has already eliminated the issue of dust, bubbles, and even thermally-induced ripples, all of which could affect the lithography beam.
Defect levels in test SRAMs made with the technology are already at production-level quality, executives said.
The two companies have also worked to develop an "ultra-low-k" dielectric, reducing the capacitance by 10 percent from the previous generation, to a "k" value of 2.4. To do so, however, has introduced another tricky technique: the introduction of tiny air pockets into the substrate. Replacing solid material with air makes the material porous, and could make it brittle. According to Kepler, however, AMD is confident that the structural integrity has been maintained.
AMD's current 65-nm chips include a technology called Dual-Stress Liners, which "strain" or pull the silicon atoms apart, allowing the transistors of the chip to switch faster. AMD's 45-nm chips will use four different stressers, increasing the stress by a factor of 1.4, AMD said.