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X48 and Elpida Hypers, 8gb, High voltage needed - Page 6 - i4memory.com - different look at memory
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Old 07-03-2012, 06:00 PM   #41
Offler
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Since the behavior of my memory si becoming a mystery to me again I will share some experience.

CAS 8-8-8-24 - System Reboots upon startup
CAS 8-7-7-21 - System is able to boot

vNB 1,41v (bit low)
vCPU 1,275v
CPU VTT: 1,270v
vMEM 1,74v

Skew Rates:
3-4-5-5

Skew model 5 proved as most stable during yesterday's testing. I just wonder what means that reboot due less intensive latencies...

Playing around with Clockgen voltage, PLL voltage and Skew modes have given me an idea of finding correct Skew model. After few tests I am sure that Skew Model 5 is the correct for the Elpida Hyper MNH chips. CPU voltage, VTT voltage and memory voltage have been set to correct values, skew model found, however system still shows some instability under load.


the last thing I also noticed is that system is not powered off after any change in bios. Since the DDR3 memory calibrates every powerup (not reboot) its a big problem. Eventually most of the "mysterious" behaviour is connected with this.

Now the question is whether the system will be able to start windows on 1,265v on Northbridge with big higher values on clock generator and PLL voltage. Althougth i doubt it, this may help to improve the power-on calibration of the memory while the NB voltage will be set to "normal" values.

Last edited by Offler; 21-03-2012 at 01:31 AM.
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Old 21-03-2012, 01:43 AM   #42
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For the next test of memory I will reconsider the memory voltage.

Currently 1,712v. Under Primetest it dropped from expected 1,67v to 1,63v. So probably I have to raise the voltage to 1,756v or a bit more.

4 dimms were unable to deliver even standard performance which equals:
1866 CL8
1600 CL7
1333 CL6

1333CL6 works, CL5 however no. 1600 CL7 was not reached yet and 1866mhz is beyond possibilities of NB and CPU.

On 1600 CL7 the system was able to POST with 3 memory sticks, but never 4. Combined load of high frequency and short latency seems to be hard to archieve with so many sticks.

Also fact that system is running almost same on voltage range from 1,41-1,49+ indicates other problem than only chipset voltage.
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Old 21-03-2012, 08:17 PM   #43
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Ok this time I have some positive results.

Some reading for reference first:

Detailed information about latencies
http://www.tweakers.fr/timings.html

Some information about DDR3 and Fly-By topology
http://www.simmtester.com/page/news/...orks+?&num=149

And some information about AData XPG:
http://www.adata.com.tw/index.php?ac...&cid=5&piid=91

a) I have to mention that my memory has 8 layer PCB with 2oz copper layers. The module PCB is very thick so its needed quite a lot of force to put them into the dimm slots. But this means great potential for tweaking.

b) 4 dimm configuration needs completely different approach as 2 dimm. On X48 its absolutely certain that Memory Controller suffers from so many chips. CAS 7 was mostly refused. Best result was that system displayed message of corrupted bios checksum.

On the other hand those memory sticks allows CR1 quite easy. It means that memory itself is of great quality, but the Memory controller is running out of breath.

c) DDR3 has twice as more banks as DDR2. My configuration also uses twice as more ranks, so overall I have 4 times more banks as similar system with ddr2 and that indeed means 4x more load on MCH.

Reducing CAS and Performance level is the easy way of improving performance. Such setting will cause Memory controller to operate faster when it comes to reading from memory. Under such heavy load its not possible.

However the more banks memory has, then Command rate has much bigger impact on overall memory performance. In case of this timing its not depending as much on memory controller as on memory itself. More layers on PCB ~ Better chance of lower Command rate. Any cooler on the memory means also additional shielding from noise ~ better chance of lower command rate.

Reading and writing are operations between memory controller and memory. Here applies factors of data strenght and skew rates and everything must be done "on time" due fly-by topology. If not MCH reads garbage even when memory contain good uncorrupted data. But there is something else.

d) Memory has also other timings which are more depending on memory itself less than on memory controller.

These are usually operations regarding precharging, refreshing and are not directly connected with read/write operations, but its the memory which is commencing some actions.

tCR - command rate. Delay between selecting chip and issuing command.

tWR - time after write before precharge. In my particular case system set this value to 22. SPD/XMP specified 15. Automatic value was far too high - decreasing performance. Too high value might cause that memory will be not precharged "on time" causing data corruption.

tWTR - time after write and before next read in the same bank - in my case in the same memory chip. Since DDR3 use single chip as single bank this time can be quite short.

tRRD - time between reads on same memory rank on different banks. SPD set this value to 1. It was working quite well. XMP set it to 3. Again was working well. Most overclockers with this board set it to 15 due bios error. Lovely isnt it. This setting is quite important when it comes to performance with so many memory chips. And again applies fact that 1 chip = 1 bank.

tRTW - similar but applies to "read to write".

In my case the goal was to give to the MCH only that read/write performance which it can handle, while memory can be tuned for faster internal operations. On DFI X48-t3rs there are few bugs and glitches in bios. Some values are not correctly set in it, automatic settings doesnt work well.

What it means for overall system performance?

Reads/writes might be better, but improvement is measurable mostly for CPU-RAM operations/calculations more than in plain read/write tests. Smaller portions of data are processed faster.
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Old 23-03-2012, 07:17 PM   #44
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Again few days of testing shows that its almost impossible to crash the system with stress generated from CPU only. Even when combined CPU/PCI-E stress testing passed its short stages in long term of system use there are very typical crashes.

System might crash when Tv tuner application is closing, or when 3d game is closing.

At this point two things happen.
- PCI-E device stops its communication with memory, or at least its not so intense
- Memory flushes a lot of data which are not currently needed

For now i have adjusted the timings a bit - now it seems that on 4dimm configuration the memory degraded by 1 class - so 1866 cl8 memory behaves like 1600 cl8 - follow the XMP settings but you have to set lower frequency.

If the problem will repeat even after corrected latencies the cause is surely in PCI-E.

Edit:
I re-read Errata of X48 . You maybe remember the "cold boot" problem with many P35 and x48 boards. Mostly it was referred as a bad overclock but its not true. Intel Errata to x48 MCH mention an issue during cold boot since december 2008. It was caused by Voltage regulator on-die of MCH which supplies the PLL mechanism for PCI-E and DMI (to not confuse it with CPU PLL in bios, its different), and as workaround is mentioned some kind of voltmod when the PLL has different source of power.

It also mentioned that same PLL mechanism might fail during bootup or Back-to-back reset anyways if some "meta-stability" conditions are met.

Obviously the chipset will always react on cold in negative way - causing PCI-E or southbridge to fail. Most workaround just reduce the ocurrence but the issue cannot be completely removed.

However there have been also reports when tight memory settings (even on DDR2 boards) caused the cold boot issue to appear more often. Extra power to the PCI-E slots provided by extra connectors onboard might supress this but still the problem is directly in northbridge.

The mysterious "meta-stability" conditions may be related to quad cores, temperatures, multiple pci-e cards, more dimm, and everything similar.

Since the higher voltage for CPU PLL and Clock Generator caused higher ocurrence of memory errors under combined PCI-E and CPU stress, but no reset if the memory dram modes were fine the reboots I currently observe are not directly result of this problem. Failed PLL locks on PCI-E/DMI always lead to reboot, but cannot cause LinX to display error.

Anyways PCI-E reference clock at 100Mhz and FSB 400Mhz may cause trouble. In most cases PCI-E and FSB runs on non-synced frequencies. If the Pci-e PLL mechanism has trouble, expecting it to have 100 percent synced performance with other devices is not good.

Last edited by Offler; 23-03-2012 at 10:31 PM.
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Old 27-03-2012, 06:05 PM   #45
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Tests with PCI-E on 106Mhz were sucessfull. Stability has not been improved, but several devices shows better responsiveness on this frequency (especially TV tuner and its CI decoder card).

Later I found theory that FSB VTT should be on value 0,176v lower than NB voltage.

For now i use these values and system is stable:

CPU 1,275v
NB 1,492v
Mem, 1,712v
VTT 1,270v

VTT which is bit lower from CPU seems a good choice for the CPU. But every NB voltage between 1,33v and 1.48v means BSOD after PCI-E stress. Never during, always after. Still it indicates voltage overshoot at time when activity ended, before the VRM correct voltages.

I tested two settings:

CPU 1,275v
VTT 1,270 and 1,25v
NB 1,44v and 1,41v

Both settings worked fine during first tests, but its needed to mention ideal ambient temperatures.

Previous stable setting shows that memory timings and dram settings are well configured. The CPU voltages have been tested many times before, but VTT and NB re-testing also seems promising.
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Old 28-03-2012, 09:56 PM   #46
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So I managed ambient temperatures to be 30C and more. At mentioned settings the system became unstable. Symptoms:

3.3v power line dropped from 3.13v to 3.02v
NB temperature has to be 57C and more
System was failing at combined test of : Prime95, TV tuner, youtube video - this time even during the test, not at turning off one of the application

I placed fan over the upper right corner of the mainboard - over memory and power connector. System was then stable even on 1,41v vNB.

The question is whether the problem is connected with memory or the power cascade temperature. The fan was set to cool both parts, however chip which manages power supply for chipset and memory was quite hot. Memory was fine...
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Old 30-04-2012, 05:30 PM   #47
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30 degrees ambient temperature.

World of Tanks with Vsync off.

NB: 1,48v and 57 c

System gone BSOD during play. I lowered NB voltages to reach healthier temperatues = stability lowered. Then I upped mem voltages a bit and system was stable then.
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