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Old 03-11-2009, 05:02 AM   #1
eva2000
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Talking 12GB A-DATA 2000X DDR3 testing

Well after my brief taste of mis-matched 12GB action, I want more So I plan to include some 12GB triple channel action in my comparison X58 triple channel kits review I have planned but as you will see from below findings some of the modules performance characteristics differed making 12GB config a bit trickier. So I'll start with testing 3x2GB configuration first on X58 then once find each individual 2GB module and 3x2GB config stability will re-test 6x2GB and then move onto the 2x2GB P55 dual channel platform for testing. This is basically I outlined approach in testing 6x2GB configs as posted here http://i4memory.com/ramdetect/. To jump straight to the start of 6x2GB tests click here.

Haven't used A-Data memory since the old A-Data PC4000 (Hynix D43) era!

They consist of 3x 4GB A-Data Xtreme Series 2000X Dual Channel kits rated at 9-9-9-24 at 1.6-1.8v. Total cost was AUD$396 for 12GB so relatively cheap per gigabyte at just under the cost of 6GB G.Skill Trident 2000Mhz C9 kits at AUD$215 per 6GB kit.

Update:

FYI, I bought another 2 sets of these as they're the cheapest per GB performance memory available in Australia right now just under 6GB Gskill Trident 2000C9 in terms of per GB costs - AUD$35.5/GB vs AUD$36.50. Two more sets of 4GB A-DATA 2000X dual channel (yes 20GB A-Data 2000X!) hoping to get some that like higher vdimm but got the opposite, one set DDR3-2000Mhz 7-8-7-24 1T at 1.58v and DDR3-2046Mhz 8-9-8-24 1T at 1.58v for memtest86+ v4.0 looping and other DDR3-2000Mhz 7-9-7-24 1T at 1.60v. Optimal vdimm getting lower and lower LOL. Unfortunately, DDR3 prices seem to be skyrocketing lately, so will be hard to get hold of other memory for my x58/p55 memory kit comparison reviews I have planned.
Specifications:
  • Module Type: 240Pin Unbuffered-DIMM Non ECC
  • Capacity Available: 4GB Dual Channel Kit (2GBx2), 2GB Dual Channel Kit (1GBx2)
  • IC Configuration: 128M x8
  • Transmission Bandwidth: 16000MB/Sec(PC3-16000)
  • Cas Latency Timing: 9-9-9-24
  • Working Voltage: 1.6V-1.8V
  • Lifetime warranty




Memtest86+ v4.0 Prelim Tests
  • Starting prelim memtest86+ v4.0 tests and interesting 4 of the 6 modules (modules #1-4) can handle 2000mhz 7-8-7-24 with 3 of them at lower QPI/DRAM but 1 needs higher QPI/DRAM (module #3).
  • The other 2 modules (modules #5 and #6) error out slightly in 7-8-7-24 at 2000mhz but handle 7-9-7-24 and 8-9-8-24 better with much lower vdimm than the other 4 modules <1.62v. More testing I guess
  • Pairing up modules #1 + #2 + #4 can do 2000mhz 7-8-7-24 around 1.68v. Pairing up modules #5 + #6 + #3 can do 2000mhz 7-9-7-24 at 1.62v and like lower vdimm over high vdimm.

3x2GB Config testing


With the above memtest86+ v4.0 findings, I decided to test the two 3x2GB pairings separately:
  • Kit 1: module #5 + #6 + #3
  • Kit 2: module #1 + #2 + #4

System:
Kit 1: module #5 + #6 + #3


Kit #1, likes lower vdimm than Kit #2 and handles 2000Mhz 7-9-7-24 and 8-9-8-24 timings well. This is very first winxp pro sp3 bench run for single Super Pi 32M - easily done at DDR3-2097Mhz 8-9-8-24 2T at 1.64v.







DDR3-2000Mhz 9-9-9-24 1T at 1.64v
(Kit 1: module #5 + #6 + #3)

Keep in mind these A-Data 2000X modules are rated for 2x2GB 2000Mhz 9-9-9-24 1T at 1.6-1.8v. The XMP profile #2 on Asus P6T6 WS Revolution sets up the system with lower bclk speed (hence low 1.35v QPI/DRAM XMP profile) with higher 12x memory multiplier 2000Mhz 9-9-9-24 1T at 1.65v with QPI/DRAM at 1.35v, but I never use XMP profiles preferring to do it all manually which is always best Adding into the mix a 3rd 2GB module for 3x2GB configuration may usually require more QPI/DRAM (cpu vtt) and Vdimm voltage.

As you push higher bclk and memory speed and use 1T as opposed to 2T, you need more VDIMM and QPI/DRAM voltage. At 20x200bclk with 10x mem multi for DDR3-2000Mhz 9-9-9-24 1T I needed QPI/DRAM = 1.4875v and VDIMM = 1.64v and to do a slight bump in IOH/IOH PCI-E volts to 1.12v and 1.52v respectively to pass HyperPi v0.99b 8x32M Pi and Single Super Pi 32M.

Note: some i7 cpus might need slight higher vcore to pass HyperPi 8x32M, than vcore needed for LinX/Prime95







more testing and results to follow

Last edited by eva2000; 24-05-2010 at 06:51 AM.
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Old 04-11-2009, 03:11 AM   #2
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System:
A-Data Xtreme Series 2000X
Kit 1: module #5 + #3 + #6

Spent some time using Memtest86+ v4.0 to figure out exactly which voltages and bioses settings effect stability and instability of this Kit 1, 3x2GB A-Data 2000X kit. I found that I get more stability switching the problematic module #3 from dimm slot #6 to slot #4 (Module #3 likes higher QPI/DRAM and Vdimm voltage than module #5 and #6).

Also found that I could tweak the stability of the problematic module #3 using DDRAM Data/CTL VREF settings for each channel A/B/C where module #3 was in dimm slot #4 (channel B). Allowing me to maintain a lower VDIMM memory voltage for module #5 and #6, but still allow module #3 to have stability. The test for this was using Memtest86+ v4.0 test #5 looping + HyperPi v0.99b 8x32M Pi test in Win7 64bit.

Moreover, tweaking subtimings also helped stabilise things. tFAW loosened from 26 to 34 and Back to Back Cas Delay (B2B) tightened from AUTO to 4 helped.

The end result is being able to pass 8x32M Pi @DDR3-2000Mhz 8-9-8-24 1T with just 1.62v and pass single Super Pi 32M @DDR3-2137Mhz 8-9-8-24 1T at 1.64v!

DDR3-2000Mhz 8-9-8-24 1T at 1.62v
(Kit 1: module #5 + #3 + #6)







DDR3-2137Mhz 8-9-8-24 1T at 1.64v
(Kit 1: module #5 + #3 + #6)










Bios settings used:
Code:

****************************
AI Tweaker
****************************
AI Overclock Tuner: Manual
CPU Ratio Setting: 20 
Intel(R) SpeedStep(TM) Tech: Disabled
BCLK Frequency: 200 & 214
PCIE Frequency: 100
DRAM Frequency: DDR3-2004Mhz & 2139Mhz
UCLK Frequency: 4009Mhz & 4278Mhz
QPI Link Data Rate: AUTO

*******************
DRAM Timing Control
*******************
DRAM CAS Latency: 8 DRAM Clock
DRAM RAS# to CAS# Delay : 9 DRAM Clock
DRAM RAS# PRE Time: 8 DRAM Clock
DRAM RAS# ACT Time: 24 DRAM Clock
DRAM RAS# to RAS# Delay: AUTO
DRAM REF Cycle Time: AUTO
DRAM WRITE Recovery Time: AUTO
DRAM READ to PRE Time: AUTO
DRAM FOUR ACT WIN Time: 34
DRAM Back-To-Back CAS# Delay: 4

DRAM Timing Mode: 1N
DRAM Round Trip Latency on CHA: AUTO
DRAM Round Trip Latency on CHB: AUTO
DRAM Round Trip Latency on CHC: AUTO

DRAM WRITE To READ Delay(DD): AUTO
DRAM WRITE To READ Delay(DR): AUTO
DRAM WRITE To READ Delay(SR): AUTO
DRAM READ To WRITE Delay (DD): AUTO
DRAM READ To WRITE Delay (DR): AUTO
DRAM READ To WRITE Delay (SR): AUTO
DRAM READ To READ Delay(DD): AUTO
DRAM READ To READ Delay(DR): AUTO
DRAM READ To READ Delay(SR): AUTO
DRAM WRITE To WRITE Delay(DD): AUTO
DRAM WRITE To WRITE Delay(DR): AUTO
DRAM WRITE To WRITE Delay(SR): AUTO

****************************
CPU Voltage: 1.30v & 1.3375v
CPU PLL Voltage: 1.80
QPI/DRAM Core Voltage: 1.53125v & 1.60v
IOH Voltage: 1.10 bios set (windows TurboV reports 1.22v or 1.30v)
IOH PCIE Voltage: 1.50
ICH Voltage: 1.10
ICH PCIE Voltage: 1.50
DRAM Bus Voltage: 1.62v and 1.64v
DRAM DATA REF Voltage on CHA: 0.485
DRAM CTRL REF Voltage on CHA: 0.485
DRAM DATA REF Voltage on CHB: 0.525
DRAM CTRL REF Voltage on CHB: 0.525
DRAM DATA REF Voltage on CHC: 0.470
DRAM CTRL REF Voltage on CHC: 0.470
****************************
Load-Line Calibration: AUTO
CPU Differential Amplitude: 1000mv
CPU Clock Skew: AUTO
CPU Spread Spectrum: Disabled
IOH Clock Skew: AUTO
PCIE Spread Spectrum: Disabled

CPU Advance Settings
C1E Support: Disabled
Hardware Prefetcher: Enabled
Adjacent Cache Line Prefetcher: Enabled
Intel (R) Virtualization Tech: Disabled
CPU TM Function: Disabled
Execute Disable Bit: Disabled
Intel (R) HT Technology: Enabled
Active Processor Cores: ALL
A20M: Disabled
Intel(R) SpeedStep(TM) Tech: Disabled
Intel (R) C-State Tech: Disabled
****************************
Express Gate: Disabled

Last edited by eva2000; 08-11-2009 at 08:55 PM.
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Old 04-11-2009, 03:11 AM   #3
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DDR3-1960Mhz 7-8-7-24 1T at 1.62v
(Kit 1: module #5 + #3 + #6)

From testing individual modules #5 and #6 they don't like DDR3-2000Mhz 7-8-7-x at all, while module #3 can handle 7-8-7-x but needs higher QPI/DRAM and vdimm voltage than modules #1, #2 and #4. So decided to see how high Kit 1 with modules #5 + #3 + #6 can go with 7-8-7-24 1T timings. I found the following from using memtest86+ v4.0 and HyperPi 8x32M tests:
  • With same tFAW = 34, B2B = 4 and DDRAM Data/CTRL VREF A/B/C tweaks as my 8-9-8-24 tests, I managed to get much less errors at DDR3-2000Mhz 7-8-7-24 1T. With tweaks around 50-65 errors, without tweaks = 10000s of errors in memtest86+ v4.0.
  • But as modules #5 and #6 like lower than 1.64v vdimm memory voltage, couldn't get DDR3-2000Mhz stable.
  • The highest I could go for memtest86+ v4.0 and HyperPi 8x32M was DDR3-1960Mhz 7-8-7-24 1T at 1.62v.












Bios settings used:
Code:

****************************
AI Tweaker
****************************
AI Overclock Tuner: Manual
CPU Ratio Setting: 20 
Intel(R) SpeedStep(TM) Tech: Disabled
BCLK Frequency: 196
PCIE Frequency: 100
DRAM Frequency: DDR3-1964
UCLK Frequency: 3929Mhz
QPI Link Data Rate: AUTO

*******************
DRAM Timing Control
*******************
DRAM CAS Latency: 7 DRAM Clock
DRAM RAS# to CAS# Delay : 8 DRAM Clock
DRAM RAS# PRE Time: 7 DRAM Clock
DRAM RAS# ACT Time: 24 DRAM Clock
DRAM RAS# to RAS# Delay: AUTO
DRAM REF Cycle Time: AUTO
DRAM WRITE Recovery Time: AUTO
DRAM READ to PRE Time: AUTO
DRAM FOUR ACT WIN Time: 34
DRAM Back-To-Back CAS# Delay: 4

DRAM Timing Mode: 1N
DRAM Round Trip Latency on CHA: AUTO
DRAM Round Trip Latency on CHB: AUTO
DRAM Round Trip Latency on CHC: AUTO

DRAM WRITE To READ Delay(DD): AUTO
DRAM WRITE To READ Delay(DR): AUTO
DRAM WRITE To READ Delay(SR): AUTO
DRAM READ To WRITE Delay (DD): AUTO
DRAM READ To WRITE Delay (DR): AUTO
DRAM READ To WRITE Delay (SR): AUTO
DRAM READ To READ Delay(DD): AUTO
DRAM READ To READ Delay(DR): AUTO
DRAM READ To READ Delay(SR): AUTO
DRAM WRITE To WRITE Delay(DD): AUTO
DRAM WRITE To WRITE Delay(DR): AUTO
DRAM WRITE To WRITE Delay(SR): AUTO

****************************
CPU Voltage: 1.25v
CPU PLL Voltage: 1.80
QPI/DRAM Core Voltage: 1.46250v
IOH Voltage: 1.24
IOH PCIE Voltage: 1.50
ICH Voltage: 1.10
ICH PCIE Voltage: 1.50
DRAM Bus Voltage: 1.62v
DRAM DATA REF Voltage on CHA: 0.485
DRAM CTRL REF Voltage on CHA: 0.485
DRAM DATA REF Voltage on CHB: 0.525
DRAM CTRL REF Voltage on CHB: 0.525
DRAM DATA REF Voltage on CHC: 0.470
DRAM CTRL REF Voltage on CHC: 0.470
****************************
Load-Line Calibration: AUTO
CPU Differential Amplitude: 1000mv
CPU Clock Skew: AUTO
CPU Spread Spectrum: Disabled
IOH Clock Skew: AUTO
PCIE Spread Spectrum: Disabled

CPU Advance Settings
C1E Support: Disabled
Hardware Prefetcher: Enabled
Adjacent Cache Line Prefetcher: Enabled
Intel (R) Virtualization Tech: Disabled
CPU TM Function: Disabled
Execute Disable Bit: Disabled
Intel (R) HT Technology: Enabled
Active Processor Cores: ALL
A20M: Disabled
Intel(R) SpeedStep(TM) Tech: Disabled
Intel (R) C-State Tech: Disabled
****************************
Express Gate: Disabled

Last edited by eva2000; 08-11-2009 at 09:07 PM.
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Old 04-11-2009, 03:11 AM   #4
eva2000
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DDR3-1900Mhz 6-8-6-24 1T at 1.62v
(Kit 1: module #5 + #3 + #6)

Testing CAS6 clocks, with 6-7-6-24 1T at 1.62v max memory frequency came to DDR3-1720Mhz (860mhz), but loosen tRCD from 7 to 8 and max memory frequency jumped to DDR3-1900Mhz 6-8-6-24 1T at 1.62v! Using same same tFAW = 34, B2B = 4 and DDRAM Data/CTRL VREF A/B/C tweaks as my 8-9-8-24 tests for HyperPi 8x32M and single Super Pi 32M.






Bios settings used:
Code:

****************************
AI Tweaker
****************************
AI Overclock Tuner: Manual
CPU Ratio Setting: 20 
Intel(R) SpeedStep(TM) Tech: Disabled
BCLK Frequency: 195
PCIE Frequency: 100
DRAM Frequency: DDR3-1900
UCLK Frequency: 3800Mhz
QPI Link Data Rate: AUTO

*******************
DRAM Timing Control
*******************
DRAM CAS Latency: 6 DRAM Clock
DRAM RAS# to CAS# Delay : 8 DRAM Clock
DRAM RAS# PRE Time: 6 DRAM Clock
DRAM RAS# ACT Time: 24 DRAM Clock
DRAM RAS# to RAS# Delay: AUTO
DRAM REF Cycle Time: AUTO
DRAM WRITE Recovery Time: AUTO
DRAM READ to PRE Time: AUTO
DRAM FOUR ACT WIN Time: 34
DRAM Back-To-Back CAS# Delay: 4

DRAM Timing Mode: 1N
DRAM Round Trip Latency on CHA: AUTO
DRAM Round Trip Latency on CHB: AUTO
DRAM Round Trip Latency on CHC: AUTO

DRAM WRITE To READ Delay(DD): AUTO
DRAM WRITE To READ Delay(DR): AUTO
DRAM WRITE To READ Delay(SR): AUTO
DRAM READ To WRITE Delay (DD): AUTO
DRAM READ To WRITE Delay (DR): AUTO
DRAM READ To WRITE Delay (SR): AUTO
DRAM READ To READ Delay(DD): AUTO
DRAM READ To READ Delay(DR): AUTO
DRAM READ To READ Delay(SR): AUTO
DRAM WRITE To WRITE Delay(DD): AUTO
DRAM WRITE To WRITE Delay(DR): AUTO
DRAM WRITE To WRITE Delay(SR): AUTO

****************************
CPU Voltage: 1.25v
CPU PLL Voltage: 1.80
QPI/DRAM Core Voltage: 1.4750v
IOH Voltage: 1.24
IOH PCIE Voltage: 1.50
ICH Voltage: 1.10
ICH PCIE Voltage: 1.50
DRAM Bus Voltage: 1.62v
DRAM DATA REF Voltage on CHA: 0.485
DRAM CTRL REF Voltage on CHA: 0.485
DRAM DATA REF Voltage on CHB: 0.525
DRAM CTRL REF Voltage on CHB: 0.525
DRAM DATA REF Voltage on CHC: 0.470
DRAM CTRL REF Voltage on CHC: 0.470
****************************
Load-Line Calibration: AUTO
CPU Differential Amplitude: 1000mv
CPU Clock Skew: AUTO
CPU Spread Spectrum: Disabled
IOH Clock Skew: AUTO
PCIE Spread Spectrum: Disabled

CPU Advance Settings
C1E Support: Disabled
Hardware Prefetcher: Enabled
Adjacent Cache Line Prefetcher: Enabled
Intel (R) Virtualization Tech: Disabled
CPU TM Function: Disabled
Execute Disable Bit: Disabled
Intel (R) HT Technology: Enabled
Active Processor Cores: ALL
A20M: Disabled
Intel(R) SpeedStep(TM) Tech: Disabled
Intel (R) C-State Tech: Disabled
****************************
Express Gate: Disabled

Last edited by eva2000; 09-11-2009 at 12:02 AM.
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Old 04-11-2009, 03:11 AM   #5
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12GB - 6x2GB A-Data 2000X
@DDR3-1702Mhz 6-7-6-24 2T at 1.62v
(Kit 1 + 2: module #1 + #5 + #4 + #3 + #2 + #6)

It paid off to individually test all 6x 2GB A-Data 2000X modules and sort out the problematic module #3 as now it's sorted out, clocking 12GB - 6x2GB config is so much easier, straight into 12GB A-Data 2000X @DDR3-1702Mhz 6-7-6-24 at 1.62v. Kept CMD Rate at auto for 2T just for starters.

Stable for Super Pi 32M at least. Need to work on HyperPi 8x32M tommorrow





click image for full screenshot





Update: Spent past 2 days working on HyperPi 8x32M Pi stability and have the following findings:
  1. To pass HyperPi 8x32M Pi you need generally more QPI/DRAM (CPU VTT) and VDIMM memory voltage than that is needed for single Super Pi 32M pass.
  2. Due to behavioural characteristics of 2 of the 6 2GB A-data 2000X modules only liking <1.64v vdimm (modules #5 and #6), trying to get 6x2GB DDR3-1600Mhz to even pass 6-7-6-24 1T or 2T timings isn't possible.
  3. Passing single 32M Pi at DDR3-1600Mhz to 1702Mhz 6-7-6-24 at 1.64v was possible, but 8x32M Pi needs more vdimm memory voltage which 2 of the 2GB modules #5 and #6 don't like >1.64v. I can get as far as 75% into 8x32M @DDR3-1600Mhz 6-7-6-24 2T at 1.64v but it will error out 3/4 of the way in.
  4. Maintaining vdimm memory voltage at <1.64v, I can pass 8x32M Pi @DDR3-1600Mhz 7-8-7-24 2T (see below).
  5. Also found with P6T6 WS Revolution board at least setting 6-7-6-24 timings resulted in much tighter Round Trip Latency (RTL) values between 51-54, versus 7-8-7-24 timings' RTL values of between 56-61. Tighter RTL values usually also require higher QPI/DRAM and VDIMM memory which for 3x2GB configs would be easy, but for 6x2GB configs to regain stability might need loosening RTL A/B/C Channel values by a delay of 6-8 which lessen the performance slightly @6-7-6-24. So for 6x2GB @DDR3-1600Mhz 7-8-7-24 2T performance taking into account RTL values, might not be that far off in terms of performance compared to 6x2GB @DDR3-1600Mhz 6-7-6-24 with looser RTL values and higher QPI/DRAM and VDIMM memory volts required.
  6. 6x2GB @DDR3-1600Mhz 6-7-6-24 was requiring >1.45v QPI/DRAM to just get into 8x32M Pi 3/4 of the way and not fully pass. If the 2 modules #5 and #6 liked higher vdimm memory voltage, I probably would of gotten 8x32M Pi to pass with >1.45v QPI/DRAM and 1.66+ VDIMM. But compare this to below 6x2GB DDR3-1600Mhz 7-8-7-24 2T only needing 1.40v QPI/DRAM and 1.62v VDIMM.




Last edited by eva2000; 11-11-2009 at 01:31 AM.
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Old 04-11-2009, 03:11 AM   #6
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12GB - 6x2GB A-Data 2000X
@DDR3-1909Mhz 7-8-7-25 2T at 1.62v
(Kit 1 + 2: module #1 + #2 + #4 + #3 + #5 + #6)

Now to test higher memory frequency with 7-8-7-25 timings at 1.62v vdimm. 1T results in ~10% more memtest86+ v4.0 reported bandwidth than 2T, but 1T was only stable for Super Pi 1M and failed 32M. 2T was much easier to pass Super Pi 32M @DDR3-1909Mhz 7-8-7-24 2T with tRFC 110, tFAW 37 and B2B 4.

Swapped module #5 and #2 places so the 6x2GB A-Data 2000X config is as follows module
  • Dimm 1 = module #1
  • Dimm 2 = module #2
  • Dimm 3 = module #4
  • Dimm 4 = module #3
  • Dimm 5 = module #5
  • Dimm 6 = module #6

System:
1T RTL A/B/C = 58/60/62






2T RTL A/B/C = 58/60/61










6x2GB = 12GB A-Data 2000X Max Validation
@DDR3-2044Mhz 7-8-7-25 2T at 1.62v / 1.5v QPI/DRAM

Managed to push 6x2GB A-Data 2000X to DDR3-2044Mhz 7-8-7-25 2T validation with 1.5v QPI/DRAM and 1.62v




Last edited by eva2000; 12-11-2009 at 04:09 AM.
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Old 04-11-2009, 03:11 AM   #7
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Now pushing 12GB A-Data 2000X to 8x32M Pi stable @DDR3-2000Mhz 8-9-8-25 2T at 1.62v vdimm with 1.50 QPI/DRAM uncore voltage with max validation at same voltages @DDR3-2112Mhz 8-9-8-25 2T!

System:
12GB - 6x2GB A-Data 2000X
@DDR3-2000Mhz 8-9-8-25 2T at 1.62v
(Kit 1 + 2: module #1 + #2 + #4 + #3 + #5 + #6)


tRFC = 110
tFAW = 38
B2B = 4

HyperPi v0.99b - 8x32M Pi



Single Super Pi 32M



Everest Bandwidth





12GB - 6x2GB A-Data 2000X
@DDR3-2112Mhz 8-9-8-25 2T at 1.62v
(Kit 1 + 2: module #1 + #2 + #4 + #3 + #5 + #6)





Last edited by eva2000; 14-11-2009 at 01:34 AM.
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Old 08-11-2009, 02:14 AM   #8
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Updated post #2 & #3 with more results and findings

Last edited by eva2000; 08-11-2009 at 09:07 PM.
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