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Old 20-06-2009, 03:55 PM   #17
3oh6
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Interesting.. but i think you need to push the bclk higher to see possible changes ? i.e. at 200bclk, 205bclk, 215bclk and 220bclk.
why do you think BCLK would have an influence?

running 200X21 2:10 7-8-7 right now BTW, just to see. i am just going to do a couple runs with 1600 strap, then 1067 if i can (which i doubt though) then 1600 strap with 1067 sub-timings. might only be able to compare 1600 and 1333 though.

Last edited by 3oh6; 20-06-2009 at 04:07 PM.
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Old 20-06-2009, 04:28 PM   #18
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Probably just my experience with DFI UT X58 past a certain bclk and things change performance wise - haven't done much testing but with DFI UT X58, the straps or RTL change with different bootup bclk set i.e. you can get tighter performance with 185bclk boot up set with 200bclk target on DFI UT X58 - the lower the bootup clock you set the more CPU VTT and vdimm you might need for same target bclk.
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Old 20-06-2009, 04:39 PM   #19
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well yeah, but that is RTL and just memory sub-timings you are talking about. i guess what i am asking is, do you think there are actual "straps" on the X58 in the traditional sense that we are use to with the previous chipsets? hidden latencies that we have no control over other than PL or the like?
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Old 20-06-2009, 04:43 PM   #20
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In traditional sense not sure. Maybe DFI engineers are just mixing the terminology up as I was told if you use a lower bootup bclk to target bclk value, you can get better performance. Maybe we need to compare performance for regular target boot clk versus boot up bclk lower than target where both subtiming and RTL values are same for both via cpu tweaker ??
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Old 20-06-2009, 04:58 PM   #21
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In traditional sense not sure. Maybe DFI engineers are just mixing the terminology up as I was told if you use a lower bootup bclk to target bclk value, you can get better performance. Maybe we need to compare performance for regular target boot clk versus boot up bclk lower than target where both subtiming and RTL values are same for both via cpu tweaker ??
that is pretty much it. i don't have a bootup and target bclk with the Classified so you are going to have to do that. assuming the DFI can adjust timings via CPU Tweaker...i thought it was just the EVGA's and GB boards that could? i could be on crack though.
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Old 20-06-2009, 05:06 PM   #22
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4/28 beta bios onwards for DFI opened up cpu tweaker support so can adjust RTL from cpu tweaker OR from bios since DFI RTL per channel adjustments are supported in DFI UT X58 4/28 and newer bioses
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Old 21-06-2009, 01:36 AM   #23
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alright, at 200x21 :: 2:10 :: 7-8-7-20 1T i ran the 1867 strap, and the 1333 strap...then the 1867 strap with 1333 strap timings aside from tWR not being the same, as it wasn't for the first set of data. like the first set of data, bandwidth and SPi 32M are all pretty much the same.

there is less than a 2 tenths of a second variance between the setups and given the difference in tWR, i stand behind my conclusion that 'MCH Strap' in the Classified BIOS adjusts nothing but memory sub-timings visible in the BIOS of CPU Tweaker. i am not doing any more testing on this, i am convinced.
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Old 21-06-2009, 01:44 AM   #24
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Interesting so not much difference on Classified
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