Rampage 3rd Year Update

[Don_Dan]

The outer slots are better than the inner ones, Asus recommends using them for high clocks as well.

[paulxmn]

By Don_Dan

The outer slots are better than the inner ones, Asus recommends using them for high clocks as well.

Correct!

[Offler]

I have heard about it - generally for all X38 and x48 based chipsets. I was wondering why its so, and why it is happenning.

Since DDR3 uses fly-by topology the timing has to be very accurate. Once the skewing with Memory is not perfect, data and instructions will be collected by MCH in incorrect order and thus corrupted, or Phase Lock is missed (data are received too early) - Instant reboot. I maybe mentioned in the past that system starts, failures few times and once its hot it works well. Temperature may affect skewing a bit.

This was happenning on "all normal" setting of skews.

The path on PCB from chipset to the memory on inner slots is bit shorter. Therefore I set skews to Advance for these slots. It does not mean that inner slots will operate sooner as the outer, but that memory controller will be ready to send/receive data by 100-150 ps earlier to slot A1 than to slot A2 so then the data flow from memory will be perfectly synchronized. I just wonder why those skews are not corrected on chipset level by default, then intel should sell those boards as 1600 compatible with all slots occupied...

Since skewing is more sensitive on higher frequencies it also perfectly reflects the initial theory...

However 400Mhz strap, as 400mhz FSB as well seems to be impossible with all dimm slots occupied.

[Offler]

Yesterday the temperature decreased at least. (38°c in shadow is a lot for this country..., now we have 25 at least )

The system had BSOD on his first boot. I changed the skew rates like this:

CMD Skew on Channel A: Normal
CLK Skew on DIMM A1: Advance 200ps
CLK Skew on DIMM A2: Normal
CTL Skew on DIMM A1: Advance 175ps
CTL Skew on DIMM A2: Normal

CMD Skew on Channel B: Normal
CLK Skew on DIMM B1: Advance 200ps
CLK Skew on DIMM B2: Normal
CTL Skew on DIMM B1: Advance 175ps
CTL Skew on DIMM B2 Normal

The system then suceeded 1 hour of Prime95 testing. Definitely the colder ambient temperatures and cold boot are affecting the memory sync when all 4 slots are occupied. Higher NB voltage is not helping directly - its just producing more heat in chip which may mask the behaviour.

The northbridge has to "warm-up" or have 55+ °C to run properly, or the skews have to be adjusted.

Strange...

[Offler]

So bit update...



With only 2 dimms the board runs fine on 1600Mhz. With four i hit the limit at 398Mhz FSB and it just cannot be crossed. No matter of NB voltage, memory voltage or whatever.

Since the memory succeeded to run 1600Mhz 6-6-6-18 I played a bit with the latencies. I realized that twice as memory means twice as addresses and thats the reason why with 8gb the CAS has to be 8. It just took more time to check whole memory.

1592Mhz 8-6-6-20 is still fine.

[Offler]

After few months another interesting find.

NB DDR Vref and all DDR Vref values were set to -27,5. I was then able to lower memory voltage from 1,75v to 1,65v and also CPU VTT voltage from 1,8v to 1,5v.

Cold boot problem was supressed and system stability improved. Additionally I was able to run timings on

1592Mhz 8-7-6-16 CR1 Performance Level 7

Memory read is then 10050mb/s, write did not changed. Not bad for 4x dimms, but the FSB frequency limit is terrible.