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Old 12-11-2009, 03:00 AM   #1
raja
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RTL

For those of you into memory tweaking on i5/i7 platforms, some info that may be of interest to you.


http://www.anandtech.com/mb/showdoc.aspx?i=3671&p=6

regards
Raja
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Old 12-11-2009, 03:17 AM   #2
eva2000
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Ooooh juicy info to chew on.. thanks Raja
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Old 12-11-2009, 03:49 AM   #3
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Hope it helps you a bit on some boards. Just move the 0.67 variable down for some boards (between 0.57 ~0.67 is what is needed mostly).

By the way, all platforms based upon this archtecture are not bound by Uncore to memory ratio. Although Bloomfield is already set to the best as it is 1:1 (when Uncore is 2X Dram), you can run it anywhere if the BIOS supports. Lynnfield gets the poo end of the stick unfortunately at 1.5X, but if the MSR's happened to be present we could have set to 2X there too.

regards
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Old 12-11-2009, 04:33 AM   #4
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Still trying to get my head around the formulas Got that excel spreadsheet handy ?

Yeah I've managed to push Uncore frequencies on air/water for DFI UT X58 to 4700mhz and Asus P6T6 WS Revo 4600mhz - interesting to go back and plug in that formula heh

DFI UT X58
http://i4memory.com/f83/i7-x58-mem-f...equency-18156/

Asus P6T6 WS Revo
http://i4memory.com/117791-post9.html

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Old 12-11-2009, 04:49 AM   #5
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http://www.mediafire.com/file/oz0moiywtyk/quick RTL calc.xlsx

Here you go, its nothing fancy. Just change the min sep delay to match where your board defaults to. You might have to scale a little at very high DRAM freqeuncies. Min Sep Delay is the delay imposed by the logixc stage of the IMC + the clock skew to the DIMM in question.

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Old 12-11-2009, 04:47 PM   #6
cstkl1
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question

isnt rtl also depends on proc and chipset

example
one 920 i have cando rtl 53 for 2050 C7
another two cant do it
and for chipset
BBSE 2000 C8 at 60,62,64
but on hyper can be done at 58,60,62

also according to ure rtl table
need to adjust min sep delay to 0.54 for classy and dfi for rtl 53 for 2k c7

so i guess the question is
for the min sep delay.. is it fix for every scaling.

and another question
same proc and setup with just voltage adjustments
4k uncore dram 2000 C7 vtt 1.4v
and 4k uncore dram 2000 C7 vtt 1.5v
both rtl are different.

Last edited by cstkl1; 12-11-2009 at 04:59 PM.
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Old 12-11-2009, 06:22 PM   #7
raja
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By cstkl1 View Post
question

isnt rtl also depends on proc and chipset

example
one 920 i have cando rtl 53 for 2050 C7
another two cant do it
and for chipset
BBSE 2000 C8 at 60,62,64
but on hyper can be done at 58,60,62

also according to ure rtl table
need to adjust min sep delay to 0.54 for classy and dfi for rtl 53 for 2k c7

so i guess the question is
for the min sep delay.. is it fix for every scaling.

and another question
same proc and setup with just voltage adjustments
4k uncore dram 2000 C7 vtt 1.4v
and 4k uncore dram 2000 C7 vtt 1.5v
both rtl are different.
Min Sep Delay is clock skew between Uncore and DRAM - this will vary according to DRAM module and board layout. Module load capacitance will change clock skew and also how tight RTL can go (a more capacitive memory module is harder for Tx to swing voltage into). Clock skew is a variable parameter - if you understand clock skew really, then you should understand this. Not all processors have Tx stages stroing enough to swing voltage, this is not the limit of Intel's RTL logic but an inability of some IMC's to swing voltage fast anough or 'well' enough.

Hope this clears this up for you. DOn't try to think too deeply if you don't understand it.

If the logic is running tighter the Uncore voltage will need to be raised, just like you did on tRD with 775.

later
Raja

Last edited by raja; 12-11-2009 at 06:29 PM.
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Old 12-11-2009, 06:56 PM   #8
cstkl1
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By raja View Post
Min Sep Delay is clock skew between Uncore and DRAM - this will vary according to DRAM module and board layout. Module load capacitance will change clock skew and also how tight RTL can go (a more capacitive memory module is harder for Tx to swing voltage into). Clock skew is a variable parameter - if you understand clock skew really, then you should understand this. Not all processors have Tx stages stroing enough to swing voltage, this is not the limit of Intel's RTL logic but an inability of some IMC's to swing voltage fast anough or 'well' enough.

Hope this clears this up for you. DOn't try to think too deeply if you don't understand it.

If the logic is running tighter the Uncore voltage will need to be raised, just like you did on tRD with 775.

later
Raja
makes sense

one more question
as this is a indicator for RTL channel A
so far RTL Channel C is +2 to Channel B
but Channel B is normally either +2 or +3 to Channel A
is there anyway to determine this other than trial and error.
this is normally the prob i get. RTL for channel B.

Last edited by cstkl1; 12-11-2009 at 07:02 PM.
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