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Old 23-04-2009, 06:29 AM   #1
eva2000
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Exclamation DFI UT X58 - tRRD, RTL, tFAW timing discussion.

From cstkl1's investigation/testing there maybe some additional tweaking we can do for linx like stability tests. It's to do with tRRD subtiming on core i7/X58 systems. According intel spec sheet tRRD only has values from 0-7 and they also determine value for core i7 memory controller timing for tWRWR which can either be 4 or 6.

When tRRD is set from 1-7 in DFI UT X58 bios it's real value is between 1-7 with tWRWR is set to 4. When tRRD is set from 8-15, tRRD real value is between 0-7 with tWRWR set to 6.

Seems cstkl1 is getting more stability when tWRWR is set to 6 by using tRRD 8-15 values in DFI UT X58 bios.

So worth trying tRRD = 14 in bios which is tRRD 6 real with tWRWR automatically set to 6.

Haven't tried this myself yet as I have my DFI UT X58 stripped down for moving from air cooling to water cooling soon

By cstkl1 View Post
make it easy

bios set 1-7 , tRRD is 1-7 tWRWR =4
bios set 8-15, tRRD is 0-7 tWRWR =6

default is
bios set 6, tRRD is 6, tWRWR = 4
so if we want to change only tWRWR to 6 only
we need to change bios set to 14. to get tRRD 6, tWRWR 6


the bios doesnt allot tRRD 0 tWRWR 4
eventhough intel spec sheet said its possible.

By cstkl1 View Post
random pagefile error
and when hang u will seee the razer battlelight still on and a few other lights but the main backlight will go off .. even mouse etc

eva just got 201mhz stable at 1n 2000mhz cl7 but dram at 1.66 but this is the freakish part

i realized my mobo likes ioh/ich to ioh analogue to be this ratio for set
1.08set/1.1set or 1.21set/1.20set and 1.31set/1.3set.

so for
2000mhz CL7 1n i need 1.31set/1.3set with vdimm 1.680set ( read 1.66)
for 2000mhz CL7 2n i need 1.21set/1.2set with vdimm 1.665( read 1.64)

i still think for ram timings is the mobo and nothing to do with proc.
so i guess my mobo just suck.. but good enough

for the full stability also depended on one more setting only which influenced the proc imc setting
testing that fully now before i post that assumption
but found this thing that felix mentioned

Code:
bios     bits9    876
tRRD     tWRWR    tRRD
 0         0       000      
 1         0       001      
 2         0       010      
 3         0       011      
 4         0       100      
 5         0       101      
 6         0       110      
 7         0       111      
 8         1       000      
 9         1       001      
10         1       010     
11         1       011     
12         1       100    
13         1       101    
14         1       110    
15         1       111
so u can see setting the bios in DFI tRRD is 0-7. and tWRWR is either 4 or 6
so setting 1-7 tWRWR is 4 , 8 ( is actually 0) -15 ( actually 7) tWRWR is 6.

found this interesting
not sure how relevant.
wonder how many other bios setting works this way.

so try setting 14/15 .. get more consistent result with tWRWR at 6.
this part i guess is cpu since tWRWR is IMC .

Last edited by eva2000; 24-04-2009 at 07:55 PM.
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Old 23-04-2009, 05:20 PM   #2
cstkl1
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eva is it possible to request dfi engineer
to make the rtl setting adjustable for channel A, B and C

i think the 1n issue is because of the C is only +1 to B

in r2e C must be min +2-3 of B

the problem is only for 1n hyperpi 32m inconsistency 16 threads is impossible atm. for 201 bclk 2010 mhz Cl7 1n
prime95 and linx doesnt seem to be fussy about it.
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Old 23-04-2009, 06:53 PM   #3
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By cstkl1 View Post
eva is it possible to request dfi engineer
to make the rtl setting adjustable for channel A, B and C

i think the 1n issue is because of the C is only +1 to B

in r2e C must be min +2-3 of B

the problem is only for 1n hyperpi 32m inconsistency 16 threads is impossible atm. for 201 bclk 2010 mhz Cl7 1n
prime95 and linx doesnt seem to be fussy about it.
I've passed your request onto DFI so fingers crossed
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Old 23-04-2009, 08:28 PM   #4
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the reason for this eva is because when i set the tWRWR to 6
the channel C becomes +1 for 1n but +2 for 2n
so stability in 2n is good
but 1n becomes worse

setting tWRWR to 4 Channel C is +2
1n is better but is inconsistent.

trying other dram setting to change C to +2 while maintaining tWRWR to 6 atm.

tWR = 9 u get C to +2
but here is the thing
tWR for different rank and different DIMM in intel spec is 1-8 while same rank is 10-22
so why the bios has 1-31??

so what are we setting actually
default is 6

Last edited by cstkl1; 23-04-2009 at 08:39 PM.
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Old 23-04-2009, 09:10 PM   #5
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I've pointed DFI to this thread, so will see what they can do.
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Old 23-04-2009, 09:32 PM   #6
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so far the most stable i ever got for 1n is
setting tRRD to 15 and tWR to 19

the reasoning for 19 is just kindda crazy. but channel C rtl is 59 which is +2 of channel B

wish dfi just give us full control of all the dram subtiming like r2e.
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Old 24-04-2009, 06:42 AM   #7
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Interesting was playing with tFAW subtiming and it seems changing tFAW value from 28 to 30 also changed RTL channel C from +1 to +2 from channel B for RTL.

With RTL manually set to +3 in bios:


tFAW = 28
RTL = 55/57/58


vs

tFAW = 30
RTL = 55/57/59



tFAW = 28



vs

tFAW =30

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Old 24-04-2009, 07:54 PM   #8
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Even weirder stuff - repeated these vcore special add % tests with a few reboots and same.

20x211 Bclk with 8x mem 844mhz 7-8-7-20 1T
  • Vcore = 1.35v + 104.1% or 104.25% vs 1.35v + 104.48%
  • Vdroop = disabled
  • tFAW = 31
  • RTL = +2

Vcore = 1.35v + 104.1% or 104.25% = RTL = 54/56/58



vs


Vcore = 1.35v + 104.48% = RTL = 54/57/58



RTL channel B & C changing with Vcore special add % ?

Last edited by eva2000; 24-04-2009 at 08:00 PM.
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