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[] AMD SSE5 Gets an Instruction-Set Expansion, Coins XOP (eXtended Operations) - - different look at memory


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Old 08-05-2009, 09:20 AM   #1
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[] AMD SSE5 Gets an Instruction-Set Expansion, Coins XOP (eXtended Operations)

AMD kept up with the SIMD processing standards Intel set by licensing its popular CPU instruction sets such as MMX, SSE, SSE3, and SSE3. The three were used as is by AMD, except for that AMD chose not to conform completely with Supplimentary SSE3, SSE4 and its revisions (SSE4.1, SSE4.2). The company devised the SSE4A instruction set to feature with its K10 micro-architecture. SSE4A is a lighter version that features LZCNT (Leading Zero Count), POPCNT (bit population count), EXTRQ/INSERTQ and MOVNTSD/MOVNTSS (Scalar streaming store instructions). What's more, the company even decided back in 2007 that it would come up with SSE5, that then Intel sought to leave development with AMD.

In due course of time, Intel started development of AVX (Advanced Vector eXtensions) that enhances processing of FPU-intensive workloads. AMD gained interest in this technology, and is looking to include it along with the originally-conceived SSE5 as a superset. The instructions that remain as part of the superset that doesn't include AVX is now referred to by AMD as XOP (eXtended OPerations). In addition to this, AMD will include FMA4 (Floating point vector Multiply-Accumulate). The new instruction sets make it to AMD's next-generation Bulldozer micro-architecture slated for 2011. Meanwhile, Intel's AVX makes it to the Sandy Bridge micro-architecture slated for 2010~11. AMD published the Programmer's Manual document on 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions, which can be read here (PDF).

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