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Old 29-07-2008, 06:49 AM   #3
eva2000
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EP45 Extreme MCH tweaking

EP45 Extreme MCH tweaking

So far with F6a bios, I haven't been able to get as much clock for clock performance out of the system as the P45 chipset seems to not like very high MCH northbridge voltage above 1.42-1.5v. So I thought I'd check to see if there's any MCH tweaks to squeeze out more performance without needing too high MCH/NB volts similar to the Asus P5B Deluxe/Commando JP Strap tweaks.

To do this, I started with the base overclock at 9x445FSB 2.0B divider 445Mhz 5-5-5-15 memory clocks with subtimings set on AUTO and Performance Enhance set to Standard. Turbo had a bit of gain in Copy bandwidth though. I then compared them with changes in only static tRead from AUTO vs 10 vs 9 and with changes in windows using memset for tREF and Pmem or Super Pi Tweaker 1.04v MCH editing tab for FED1403F address.

I used Everest Ultimate 4.50.1469 memory bandwidth test to compare the changes.

Configurations tested:
  1. 4005Mhz - 9x445FSB 1:1 445Mhz 5-5-5-15 Performance Enhanced = Standard | Static tRead: Auto (vNB = 1.30v)
  2. 4005Mhz - 9x445FSB 1:1 445Mhz 5-5-5-15 Performance Enhanced = Turbo | Static tRead: Auto (vNB = 1.30v)
  3. 4005Mhz - 9x445FSB 1:1 445Mhz 5-5-5-15 Performance Enhanced = Standard | Static tRead: 10 (vNB = 1.30v)
  4. 4005Mhz - 9x445FSB 1:1 445Mhz 5-5-5-15 Performance Enhanced = Standard | Static tRead: 10 Tweak 1 (vNB = 1.30v)
  5. 4005Mhz - 9x445FSB 1:1 445Mhz 5-5-5-15 Performance Enhanced = Standard | Static tRead: 9 (vNB = 1.40v)
  6. 4005Mhz - 9x445FSB 1:1 445Mhz 5-5-5-15 Performance Enhanced = Standard | Static tRead: 9 Tweak 1 (vNB = 1.40v)
  7. 4005Mhz - 9x445FSB 1:1 445Mhz 5-5-5-15 Performance Enhanced = Standard | Static tRead: 9 Tweak 1 + 2 (vNB = 1.40v)
  8. 8x500FSB 2.40B 5:6 5-5-5-15 Std tRead = 10 (vNB = 1.42v)
  9. 8x500FSB 2.40B 5:6 5-5-5-15 Turbo tRead = 9 (vNB = 1.50v)
  10. 8x500FSB 2.40B 5:6 5-5-5-15 Turbo tRead = 9 Tweak 1 (vNB = 1.50v)
  11. 8x500FSB 2.40B 5:6 5-5-5-15 Turbo tRead = 9 Tweak 1+2 (vNB = 1.50v)

Click image for full results including L1 and L2 cache bandwidth and latencies.






Notes:
  • Tweak 1 = FED1403F MCH address change from 65 to 60
  • Tweak 2 = Memset change tREF to 16383T
  • tRead of 9 and tighter needed vNB of 1.40v to boot
  • The tRead phase 0 to 3 adjustments couldn't be advanced on any channels at tRead 10 with just 1.30v NB volts

The result is some success I think as you can see the static tRead 10 + Tweak 1 required only 1.30v NB volts to get similar performance as static tRead 9 which required 1.40v NB volts. More testing is needed at even higher FSB and tighter timings though.

9x445FSB 1:1 5-5-5-15

tRead AUTO (left) & 10 (right)


tRead 10 + Tweak 1 (left) & 9 (right)


tRead 9 + Tweak 1 (left) & 9 + Tweak 1 + 2 (right)


8x500FSB 5:6 5-5-5-15

tRead 9 + Tweak 1 + 2



Super Pi 32M v1.50

9x445FSB 1:1 5-5-5-15

tRead 10 = 12min 20.843s
vs
tRead 9 Tweak 1+2 = 12min 09.859s

8x500FSB 5:6 5-5-5-15

tRead 10 = 11min 44.141s
vs
tRead 9 Tweak 1+2 = 11min 34.563s



Bios settings used for 9x445FSB 1:1 :
Code:
GIGABYTE GA-EP45_EXTREME
MB Intelligent Tweaker(M.I.T.)
Robust Graphics Booster:  AUTO
CPU Clock Ratio: 9x
Fine CPU Clock Ratio: [+0.0]
CPU Frequency: Mhz: 4.00Ghz

Clock Chip Control 
Standard Clock Control
CPU Host Clock Control: [Enabled]
CPU Host Frequency(Mhz): 445 Mhz
PCI Express Frequency(Mhz): 100 Mhz
C.I.A. 2: [Disabled]

Advanced Clock Control [Press Enter]
CPU Clock Drive: 800mv
PCI Express Clock Drive: 700mv
CPU Clock Skew: 0ps
MCH Clock Skew: 0ps

DRAM Performance Control
Performance Enhance: [Standard]
Extreme Memory Profile (X.M.P.): Disabled 
(G)MCH Frequency Latch: [Auto]
System Memory Multiplier: 2.0B
Memory Frequency (Mhz): 890Mhz
DRAM Timing Selectable: [Manual]
Standard Timing Control
CAS Latency Time: 5
tRCD: 5
tRP:  5
tRAS: 15 

Advanced Timing Control [Press Enter]
tRRD: AUTO
tWTR: AUTO
tWR: AUTO
tRFC: AUTO
tRTP: AUTO
Command Rate (CMD): AUTO

Channel A
Static tRead Value: AUTO vs 10 vs 9
tRD Phase0 Adjustment: Auto
tRD Phase1 Adjustment: Auto
tRD Phase2 Adjustment: Auto
tRD Phase3 Adjustment: Auto
Trd2rd(Different Rank).: Auto 
Twr2wr(Different Rank): Auto 
Twr2rd(Different Rank): Auto 
Trd2wr(Same/Diff Rank): Auto 
Dimm1 Clock Skew Control: Auto  ps
Dimm2 Clock Skew Control: Auto  ps

Channel B
Static tRead Value: Auto vs 10 vs 9

tRD Phase0 Adjustment: Auto
tRD Phase1 Adjustment: Auto
tRD Phase2 Adjustment: Auto
tRD Phase3 Adjustment: Auto
Trd2rd(Different Rank).: Auto 
Twr2wr(Different Rank): Auto 
Twr2rd(Different Rank): Auto 
Trd2wr(Same/Diff Rank): Auto 
Dimm1 Clock Skew Control: Auto  ps
Dimm2 Clock Skew Control: Auto  ps

Motherboard Voltage Control

CPU Vcore: 1.300v
CPU Termination | 1.200V: 1.240v
CPU PLL | 1.500V: 1.500 v
CPU Reference | 0.760V: 0.786v
CPU Reference2 | 0.800V: 0.805v

MCH Core | 1.100V: 1.300v (tRead AUTO and 10) vs 1.400v (tRead 9)
MCH Reference | 0.800V: 0.765v
MCH/DRAM Ref | 0.900V: AUTO v
ICH I/O | 1.500V: AUTO v
ICH Core | 1.100V: AUTO v

DRAM Voltage | 1.800V: 2.000v / 2.100v
DRAM Termination | 0.900V: AUTO v
Channel A Reference | 0.900V: AUTO v
Channel B Reference | 0.900V: AUTOv



[b]Advanced Bios Features[b]
Limit CPUID Max. to 3: [Disabled]
No-Execute Memory Protect: [Disabled]
CPU Enhanced Halt (C1E): [Disabled]
C2/C2E State Support: [Disabled]
x C4/C4E State Support: [Disabled]
CPU Thermal Monitor 2(TM2): [Disabled]
CPU EIST Function: [Disabled]
Virtualization Technology.: [Disabled]

Last edited by eva2000; 13-08-2008 at 04:35 AM.
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