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Old 22-08-2006, 10:39 PM   #5
eva2000's PC Specs
Join Date: Jul 22 2004
Location: Brisbane, Australia
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Re: Intel Core 2 Duo E6600 Conroe + Asus P5W DH Deluxe

Analysis of P5W DH memory 4:5 and 2:3 dividers

I've been messing around with 4:5 and 2:3 dividers are lower FSB clocks and checking memset to see what values are being set since i'd having issues in memtest86+ v1.65 test #7 errors in high fsb 4:5 mode.

In 2:3 I maxed out my memory @542mhz 4-4-4-12 at 2.4v which showed the following memset timing values

tRFC = 42
tRD = 6
Write to Precharge Cmd = 13
Write to Read Cmd = 10
Read-Write Turnaround CLKs = 8
Write-Read Turnaround CLKs = 6
tRTP = 5

Now in 4:5 mode the only changes in memset are for:

tRFC = 35
Write to Precharge Cmd = 12

As you see it's tighter than at 2:3 set memset timings. So I booted into windows from bios at 9x378fsb 4:5 with memory at 472.5mhz 4-4-4-12 at 2.3v and used clockgen to clock up incrementally to test the max FSB:MEM clocks and find out how loosening these memset options will effect max 4:5 FSB:MEM clocks.

Using Systool dual 32M PI (cpu test), I managed to use Clockgen to raise FSB from 378fsb to 394fsb (493mhz 4-4-4-12 for memory) before it started to fail/error out. This was still with default memset timings where tRD = 6. I then raised tRD from 6 to 7, and easily managed to raise FSB from 394fsb to 400fsb (500mhz 4-4-4-12 for memory) and pass the tests without errors!

With tRD = 7, i could even tighten tRFC from 35 down to 20 with no problems.

@3600Mhz - 9x400fsb 4:5 500mhz 4-4-4-8 at 2.3v (more vdimm allows to handle tigher tRFC values but tRD needed 7)

So it does seem for 4:5 divider the culprit maybe tRD = 6. Now some folks managed to get high 4:5 clocks on P5W DH and I suspect this due to higher voltages or voltage mods on vdimm and vMCH as these two voltages help the memory/MCH handle the tight tRD value of 6 apparently. With enough voltage you could clock the memory higher for 4:5 ratio

Seems to me that for 975x chipset, both the max FSB limits and inability to handle high fsb in 4:5 and 2:3 dividers all comes down to tRD being too tight at 6. How far you can take your FSB and clocks in async divider mode, depend on:

1. MCH/NB quality and latencies
2. MCH/NB cooling - better MCH/NB cooling = higher FSB and higher memory clocks
3. MCH Voltage
4. Memory modules used - if the memory can handle tRD = 6 well then it will clock higher, allowing high FSB
5. vDIMM - memory voltage helps memory handle tighter advance timings, thus higher max FSB

Update: March 19, 2007

Since I posted that info, i've had a chance to play with Asus P5B Deluxe, Asus 680i Striker extreme, DFI ICFX3200 and Abit AB9 QuadGT and the above comments hold true for all platforms I tested - to varying degrees.

You could add a 6th factor to the above 5 or elaboration of 1st factor, that is how each brand/model of motherboard tunes or tweaks their NB can have an effect.

i.e. if Asus P5B Deluxe has very tight NB strap and latencies for clock for clock faster times than Gigabyte 965P boards, then raising NB volts on P5B Deluxe may have a more beneficial effect than on Gigabyte 965P board.

The Gigabyte 965P may have little or no effect on improving FSB or ram clocks when NB volts is raised compared to P5B Deluxe as NB strap and latencies aren't that tight.
Further proof, i upped vdimm to 2.4v with vMCH still at 1.65v and booted into windows at 9x390fsb 4:5 487mhz 4-4-4-8. Using memset loosened timings to match that of default 2:3 divider tRFC = 42 and Write to Precharge Cmd = 13 but loosened tRD from 6 to 7. Managed to clock memory right up to 540mhz 4-4-4-8 at 2.4v without problems for single 32M and 538mhz 4-4-4-8 for dual 32M.

Single 32M @540mhz 4-4-4-8 at 2.4v

Dual 32M @538mhz 4-4-4-8 at 2.4v

And now tightening the rest of memset timings while tRD = 7

Last edited by eva2000; 19-03-2007 at 11:43 PM.
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