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Old 04-11-2009, 02:11 AM   #2
eva2000
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Join Date: Jul 22 2004
Location: Brisbane, Australia
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System:
A-Data Xtreme Series 2000X
Kit 1: module #5 + #3 + #6

Spent some time using Memtest86+ v4.0 to figure out exactly which voltages and bioses settings effect stability and instability of this Kit 1, 3x2GB A-Data 2000X kit. I found that I get more stability switching the problematic module #3 from dimm slot #6 to slot #4 (Module #3 likes higher QPI/DRAM and Vdimm voltage than module #5 and #6).

Also found that I could tweak the stability of the problematic module #3 using DDRAM Data/CTL VREF settings for each channel A/B/C where module #3 was in dimm slot #4 (channel B). Allowing me to maintain a lower VDIMM memory voltage for module #5 and #6, but still allow module #3 to have stability. The test for this was using Memtest86+ v4.0 test #5 looping + HyperPi v0.99b 8x32M Pi test in Win7 64bit.

Moreover, tweaking subtimings also helped stabilise things. tFAW loosened from 26 to 34 and Back to Back Cas Delay (B2B) tightened from AUTO to 4 helped.

The end result is being able to pass 8x32M Pi @DDR3-2000Mhz 8-9-8-24 1T with just 1.62v and pass single Super Pi 32M @DDR3-2137Mhz 8-9-8-24 1T at 1.64v!

DDR3-2000Mhz 8-9-8-24 1T at 1.62v
(Kit 1: module #5 + #3 + #6)







DDR3-2137Mhz 8-9-8-24 1T at 1.64v
(Kit 1: module #5 + #3 + #6)










Bios settings used:
Code:

****************************
AI Tweaker
****************************
AI Overclock Tuner: Manual
CPU Ratio Setting: 20 
Intel(R) SpeedStep(TM) Tech: Disabled
BCLK Frequency: 200 & 214
PCIE Frequency: 100
DRAM Frequency: DDR3-2004Mhz & 2139Mhz
UCLK Frequency: 4009Mhz & 4278Mhz
QPI Link Data Rate: AUTO

*******************
DRAM Timing Control
*******************
DRAM CAS Latency: 8 DRAM Clock
DRAM RAS# to CAS# Delay : 9 DRAM Clock
DRAM RAS# PRE Time: 8 DRAM Clock
DRAM RAS# ACT Time: 24 DRAM Clock
DRAM RAS# to RAS# Delay: AUTO
DRAM REF Cycle Time: AUTO
DRAM WRITE Recovery Time: AUTO
DRAM READ to PRE Time: AUTO
DRAM FOUR ACT WIN Time: 34
DRAM Back-To-Back CAS# Delay: 4

DRAM Timing Mode: 1N
DRAM Round Trip Latency on CHA: AUTO
DRAM Round Trip Latency on CHB: AUTO
DRAM Round Trip Latency on CHC: AUTO

DRAM WRITE To READ Delay(DD): AUTO
DRAM WRITE To READ Delay(DR): AUTO
DRAM WRITE To READ Delay(SR): AUTO
DRAM READ To WRITE Delay (DD): AUTO
DRAM READ To WRITE Delay (DR): AUTO
DRAM READ To WRITE Delay (SR): AUTO
DRAM READ To READ Delay(DD): AUTO
DRAM READ To READ Delay(DR): AUTO
DRAM READ To READ Delay(SR): AUTO
DRAM WRITE To WRITE Delay(DD): AUTO
DRAM WRITE To WRITE Delay(DR): AUTO
DRAM WRITE To WRITE Delay(SR): AUTO

****************************
CPU Voltage: 1.30v & 1.3375v
CPU PLL Voltage: 1.80
QPI/DRAM Core Voltage: 1.53125v & 1.60v
IOH Voltage: 1.10 bios set (windows TurboV reports 1.22v or 1.30v)
IOH PCIE Voltage: 1.50
ICH Voltage: 1.10
ICH PCIE Voltage: 1.50
DRAM Bus Voltage: 1.62v and 1.64v
DRAM DATA REF Voltage on CHA: 0.485
DRAM CTRL REF Voltage on CHA: 0.485
DRAM DATA REF Voltage on CHB: 0.525
DRAM CTRL REF Voltage on CHB: 0.525
DRAM DATA REF Voltage on CHC: 0.470
DRAM CTRL REF Voltage on CHC: 0.470
****************************
Load-Line Calibration: AUTO
CPU Differential Amplitude: 1000mv
CPU Clock Skew: AUTO
CPU Spread Spectrum: Disabled
IOH Clock Skew: AUTO
PCIE Spread Spectrum: Disabled

CPU Advance Settings
C1E Support: Disabled
Hardware Prefetcher: Enabled
Adjacent Cache Line Prefetcher: Enabled
Intel (R) Virtualization Tech: Disabled
CPU TM Function: Disabled
Execute Disable Bit: Disabled
Intel (R) HT Technology: Enabled
Active Processor Cores: ALL
A20M: Disabled
Intel(R) SpeedStep(TM) Tech: Disabled
Intel (R) C-State Tech: Disabled
****************************
Express Gate: Disabled

Last edited by eva2000; 08-11-2009 at 07:55 PM.
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