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Gigabyte GA-EP45 Extreme rev1.0 Review

This is a discussion on Gigabyte GA-EP45 Extreme rev1.0 Review within the Gigabyte Intel Motherboard / CPU forums, part of the Intel motherboards / CPU category; Thanks to Gigabyte, I'll be checking out their latest motherboard offerings starting with their Gigabyte GA-EP45 Extreme based on the ...

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Old 29-07-2008, 06:43 AM   #1 (permalink)
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Cool Gigabyte GA-EP45 Extreme rev1.0 Review

Thanks to Gigabyte, I'll be checking out their latest motherboard offerings starting with their Gigabyte GA-EP45 Extreme based on the new Intel P45 chipset

Photos:




More photos here.

Links & Downloads:
Notes & Tips:

I'm going to skip most of formailities and dive right into it starting with what I'd consider the most important points I've come across in the first 24hrs of using this GA-EP45 Extreme motherboard.

System:
  • E8500 Q740A479T 2L7 / 1313
  • CPU Cooling: Dtek Fuzion Rad Tower Box
  • Gigabyte GA-EP45 Extreme rev 1.0 F6a bios
  • 128MB Gainward FX5200 PCI
  • 2x1GB Crucial Ballistix PC2-8500 dual channel kit
  • Memory cooling: 120x25mm Thermaltake 81cfm fan
  • 74GB Western Digital Raptor
  • Pioneer 215 DVD-RW
  • 1200W Silverstone OP1200
  • WinXP Pro SP2 Nlite Fully Updated.

Important info gained from first 24hrs of GA-EP45 Extreme usage with F6a bios:
  1. Any memory inserted into dimm 2+4 slots result in continuous reboot so I used dimm 1+3 slot until I figure out what is wrong with dimm 2+4 slots
  2. I intended to use Thermalright Ultra 120 Extreme air heatsink with the EP45 Extreme, but found out that there's 5 components on backside of motherboard near one mounting hole that touch and get in the way of the Thermalright Ultra 120 Extreme backplate. Rather than risk crushing these components, I opted to use Dtek Fuzion waterblock without a backplate for cpu cooling. However, some folks have reported installing the Thermalright Ultra 120 Extreme and backplate disregarding the 5 components and haven't heard any issues yet. But just be aware of this
  3. For max FSB clocking on dual core cpu (I used E8500 Q740A479T), the 4 options in Advance Clock Control menu are key - CPU Clock Drive, PCI Express Clock Drive, CPU Clock Skew and MCH Clock skew. Bumping them from 800mv, 700mv, 0ps, 0ps to 1000mv, 1000mv, 400ps, 400ps respectively, allowed my FSB wall to jump from >450FSB (continuous reboot/reset) to 575FSB for memtesting (yet to test in windows). Of course I had to tune other voltages, but it was these 4 options were key to bypass the continuous reboot/reset issue.
  4. Tuning the CPU Termination voltage (CPU VTT or CPU FSB on some boards) along with CPU Reference, CPU Reference 2 and MCH Reference is the next most important factor in achieving max FSB.
  5. CPU Reference, CPU Reference 2 and MCH Reference automatically move and adjust at the predefined fixed ratio with CPU Termination voltage. For example, at 1.2v default CPU Termination voltage, CPU Reference/Reference2 are 0.760v and 0.800v respectively. That would equate to GTL reference ratio of 0.760/1.2 = 0.6333 and 0.800/1.20 = 0.6666 respectively. The MCH Reference volt defaults to 0.800v which is also 0.6666 GTL Reference ratio for MCH. Now if you increased CPU Termination voltage from 1.2v to 1.3v without adjusting CPU Reference, CPU Reference 2 and MCH Reference, then the bios will automatically bump CPU Reference, CPU Reference 2 and MCH Reference voltages to maintain the exact GTL reference ratio for CPU Reference, CPU Reference 2 and MCH Reference to 0.6333, 0.6666 and 0.6666 respectively. Thus you can alter the fixed ratio against CPU Termination voltage by manually adjusting the voltages for CPU Reference, CPU Reference 2 and MCH Reference.
  6. On boards like DFI and Asus these are the same as CPU 0/1/2/4 GTL Reference and NB GTL Reference voltage tweaks and follow similarly in that dual core and quad core cpus like a specific ratio for CPU Reference and MCH (NB) References i.e. between ~0.61 and ~0.67.
  7. I found for my E8500 so far they like CPU Reference, CPU Reference 2 and MCH Reference GTL reference ratios of approximately, 0.635, 0.648 and 0.617 respectively to maintain memtest stability especially test #7 looping (good initial indicator of whether you'd be able to boot into windows to even pull of some semi-stable benching).
  8. There seems to be alot of double auto shut-down/reboot and reset to default cpu FSB (333FSB) with this board - some are due to bios setting changes i.e. FSB, memory timings etc but there's also some due to incorrect settings/clocks or even voltage changes so it's hard to separate and identify which instance is attributed to what changes. More testing will be needed to figure this out
  9. With 2x1GB Crucial Ballistix PC2-8500 double sided Micron D9GMH modules, if i set tRFC too loose 56-72 i get more memtest86+ v2.01 test #5 errors at unstable mem clocks than if I set tRFC at 42!
  10. In terms of memory bandwidth, if you leave Static tRead value for both channel A & B on AUTO, the value stated might not be the actual value I don't think. Experiment with setting the Static tRead value to +1 value of what is show in bios and you may even see a bandwidth boost in memtest86+ v2.01 and windows. For example at 7.5x500FSB 2.0B 4-4-4-12 with Static tRead on AUTO bios says value is 8 and memtest86+ v2.01 bandwidth is approximately 5158MB/s, but if i manually set the Static tRead +1 above the shown value at 9, memtest86+ v2.01 reports 5466MB/s bandwidth. Update: seems tRead value shown in bios when set to AUTO isn't any where near the real value. AUTO must actually be at least +3 or +4 more than the displayed value if my tests here are anything to go by.

Bios Screenshots
Will upload later....

Bios template
Updated F6H bios template

Code:
GIGABYTE GA-EP45_EXTREME
MB Intelligent Tweaker(M.I.T.)
Robust Graphics Booster:  AUTO
CPU Clock Ratio: 9x
Fine CPU Clock Ratio: [+0.5]
CPU Frequency: Mhz

Clock Chip Control 
Standard Clock Control
CPU Host Clock Control: [Enabled]
CPU Host Frequency(Mhz): 333 Mhz
PCI Express Frequency(Mhz): 100 Mhz
C.I.A. 2: [Disabled]

Advanced Clock Control [Press Enter]
CPU Clock Drive: mv
PCI Express Clock Drive: mv
CPU Clock Skew: ps
MCH Clock Skew: ps

DRAM Performance Control
Performance Enhance: [Turbo]
Extreme Memory Profile (X.M.P.): 
(G)MCH Frequency Latch: [Auto]
System Memory Multiplier:
Memory Frequency (Mhz): Mhz
DRAM Timing Selectable: [Manual]
Standard Timing Control
CAS Latency Time: 
tRCD: 
tRP:  
tRAS:  

Advanced Timing Control [Press Enter]
tRRD:
tWTR:
tWR:
tRFC:
tRTP:
Command Rate (CMD):

>>>>> Channel A
Channel A Timing Settings: [Press Enter]
Static tRead Value: Auto
tRD Phase0 Adjustment: Auto
tRD Phase1 Adjustment: Auto
tRD Phase2 Adjustment: Auto
tRD Phase3 Adjustment: Auto
Trd2rd(Different Rank).: Auto 
Twr2wr(Different Rank): Auto 
Twr2rd(Different Rank): Auto 
Trd2wr(Same/Diff Rank): Auto 
Dimm1 Clock Skew Control: Auto  ps
Dimm2 Clock Skew Control: Auto  ps

Channel A Driving Settings: [Press Enter]
Driving Strength Profile: AUTO/667Mhz/800Mhz/1066Mhz/OC-1200/OC-1333

Data Driving Pull-Up Level:
Cmd Driving Pull-Up Level:
Ctrl Driving Pull-Up Level:
Clk Driving Pull-Up Level:

Data Driving Pull-Down Level:
Cmd Driving Pull-Down Level:
Ctrl Driving Pull-Down Level:
Clk Driving Pull-Down Level:

>>>>> Channel B
Channel B Timing Settings: [Press Enter]
Static tRead Value: Auto
tRD Phase0 Adjustment: Auto
tRD Phase1 Adjustment: Auto
tRD Phase2 Adjustment: Auto
tRD Phase3 Adjustment: Auto
Trd2rd(Different Rank).: Auto 
Twr2wr(Different Rank): Auto 
Twr2rd(Different Rank): Auto 
Trd2wr(Same/Diff Rank): Auto 
Dimm1 Clock Skew Control: Auto  ps
Dimm2 Clock Skew Control: Auto  ps

Channel B Driving Settings: [Press Enter]
Driving Strength Profile: AUTO/667Mhz/800Mhz/1066Mhz/OC-1200/OC-1333

Data Driving Pull-Up Level:
Cmd Driving Pull-Up Level:
Ctrl Driving Pull-Up Level:
Clk Driving Pull-Up Level:

Data Driving Pull-Down Level:
Cmd Driving Pull-Down Level:
Ctrl Driving Pull-Down Level:
Clk Driving Pull-Down Level:

Motherboard Voltage Control

CPU Vcore: v
CPU Termination | 1.200V: v
CPU PLL | 1.500V: v
CPU Reference | 0.760V: v
CPU Reference2 | 0.800V: v

MCH Core | 1.100V: v
MCH Reference | 0.800V: v
MCH/DRAM Ref | 0.900V: v
ICH I/O | 1.500V: v
ICH Core | 1.100V: v

DRAM Voltage | 1.800V: v
DRAM Termination | 0.900V: v
Channel A Reference | 0.900V: v
Channel B Reference | 0.900V: v

Advanced Bios Features
Limit CPUID Max. to 3: [Disabled]
No-Execute Memory Protect: [Disabled]
CPU Enhanced Halt (C1E): [Disabled]
C2/C2E State Support: [Disabled]
x C4/C4E State Support: [Disabled]
CPU Thermal Monitor 2(TM2): [Disabled]
CPU EIST Function: [Disabled]
Virtualization Technology.: [Disabled]

Integrated Peripherals
SATA RAID/AHCI Mode: [Disabled]
SATA Port0-3 Native Mode: [Disabled]
USB Controller: [Enabled]
USB 2.0 Controller: [Enabled]
USB Keyboard Support: [Disabled]
USB Mouse Support: [Disabled]
Legacy USB storage detect: [Enabled]
Results:
Seems I have slightly better max FSB bootable (not stable) than Asus boards at around 570-575FSB bootable 1:1 with 2.0B divider but need loosened mem timings of 5-7-7-24 right now. Yet to try other dividers as started testing with 1:1 2.0B divider first and it's pretty hard to hit high FSB with mem timings of 5-5-5-15 or 4-4-4-15 which both need around 0.10v to 0.18v more vdimm than on Asus P35 and /DFI P35/X38/X48 chipsets.

Managed to pull off personal best max FSB Super Pi 1M bench run @7x564FSB 4-4-4-15 but needed PL10 and 2.48v to do it !

Super Pi 1M


Everest Bandwidth & Chipset
Seems that read memory bandwidth and latency are quite low for 564Mhz 4-4-4-15 memory clocks and timings but write and copy bandwidth look decent. Probably due to the loosened Static tRead (what DFI/Asus users would of known as tRD or performance level) of around 10. Gigabyte Easytune6 utility misreports, the values set in bios for CPU Reference, CPU Reference2 and MCH Reference. Easytune6 reports the default normal values instead they should be 0.853, 0.868 and 0.828 respectively.



Bios settings used:
Code:
GIGABYTE GA-EP45_EXTREME
MB Intelligent Tweaker(M.I.T.)
Robust Graphics Booster:  AUTO
CPU Clock Ratio: 7x
Fine CPU Clock Ratio: [+0.0]
CPU Frequency: Mhz: 3.94Ghz

Clock Chip Control 
Standard Clock Control
CPU Host Clock Control: [Enabled]
CPU Host Frequency(Mhz): 564 Mhz
PCI Express Frequency(Mhz): 103 Mhz
C.I.A. 2: [Disabled]

Advanced Clock Control [Press Enter]
CPU Clock Drive: 1000mv
PCI Express Clock Drive: 1000mv
CPU Clock Skew: 300ps
MCH Clock Skew: 300ps

DRAM Performance Control
Performance Enhance: [Turbo]
Extreme Memory Profile (X.M.P.): 
(G)MCH Frequency Latch: [Auto]
System Memory Multiplier: 2.0B
Memory Frequency (Mhz): 1128Mhz
DRAM Timing Selectable: [Manual]
Standard Timing Control
CAS Latency Time: 4
tRCD: 4
tRP:  4
tRAS: 15 

Advanced Timing Control [Press Enter]
tRRD: 4
tWTR: 6
tWR: 8
tRFC: 42
tRTP: 4
Command Rate (CMD): AUTO

Channel A
Static tRead Value: 10
tRD Phase0 Adjustmen: Auto
tRD Phase1 Adjustment: Auto
tRD Phase2 Adjustment: Auto
tRD Phase3 Adjustment: Auto
Trd2rd(Different Rank).: Auto 
Twr2wr(Different Rank): Auto 
Twr2rd(Different Rank): Auto 
Trd2wr(Same/Diff Rank): Auto 
Dimm1 Clock Skew Control: Auto  ps
Dimm2 Clock Skew Control: Auto  ps

Channel B
Static tRead Value: 10

tRD Phase0 Adjustmen: Auto
tRD Phase1 Adjustment: Auto
tRD Phase2 Adjustment: Auto
tRD Phase3 Adjustment: Auto
Trd2rd(Different Rank).: Auto 
Twr2wr(Different Rank): Auto 
Twr2rd(Different Rank): Auto 
Trd2wr(Same/Diff Rank): Auto 
Dimm1 Clock Skew Control: Auto  ps
Dimm2 Clock Skew Control: Auto  ps

Motherboard Voltage Control

CPU Vcore: 1.325v
CPU Termination | 1.200V: 1.340v
CPU PLL | 1.500V: 1.500 v
CPU Reference | 0.760V: 0.853v
CPU Reference2 | 0.800V: 0.868v

MCH Core | 1.100V: 1.440v
MCH Reference | 0.800V: 0.828v
MCH/DRAM Ref | 0.900V: AUTO v
ICH I/O | 1.500V: AUTO v
ICH Core | 1.100V: AUTO v

DRAM Voltage | 1.800V: 2.480v
DRAM Termination | 0.900V: AUTO v
Channel A Reference | 0.900V: AUTO v
Channel B Reference | 0.900V: AUTOv

Advanced Bios Features
Limit CPUID Max. to 3: [Disabled]
No-Execute Memory Protect: [Disabled]
CPU Enhanced Halt (C1E): [Disabled]
C2/C2E State Support: [Disabled]
x C4/C4E State Support: [Disabled]
CPU Thermal Monitor 2(TM2): [Disabled]
CPU EIST Function: [Disabled]
Virtualization Technology.: [Disabled]

Last edited by eva2000; 03-10-2008 at 03:06 AM.
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Old 29-07-2008, 06:49 AM   #2 (permalink)
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5:6 Memory Divider (2.40B) Testing

5:6 Memory Divider (2.40B) Testing

Starting to get the hang of how memory interacts with EP45 Extreme motherboard's bios settings, so thought I'd check out the memory dividers.
  1. First up is 2.40B divider (5:6) and it seems by default the Static tRead value that is set by default for 2.4B divider is too tight. At 9.5x333FSB 2.40B 400Mhz 5-5-5-15 at 2.00v vdimm with CPU VTT and MCH set at 1.20v and 1.30v respectively, Static tRead value is automatically set to 7 according to what the bios says and results in a power down/reboot and reset cycle when you save and exit bios. Probably, due to the low MCH voltage somewhat.
  2. So I had to loosen Static tRead manually from 7 to 9 for both Channel A & B in bios for the system to even boot and memory clocked all the way to 565mhz 5-5-5-15 at 2.00v and 593mhz 5-5-5-15 at 2.16v with Static tRead of 9 for memtest86+ v2.01 testing.
  3. As I continued to push the FSB with 2.4B divider, I got to stage where 500FSB with 600mhz 5-5-5-15 needed loosening Static tRead to 10 for both channels as well as manually pulling up (loosening), tRD Phase 0 to 3 Adjustments for Channel B as bios automatically was pulling down and tightening tRD Phase 0, 2 and 3 Adjustments causing minor memtest86+ v2.01 test #5 looping errors.
  4. At 500FSB 600mhz 5-5-5-15, raising MCH voltage helped reduced the number of memtest86+ v2.01 test #5 looping errors at the same set vdimm of 2.24v. MCH voltage ended up at 1.42v which seems like a sweet spot for this board as i tried 1.48v and 1.50v with less stability. Some folks have stated CPU Termination (CPU VTT) and MCH are tied and better to have voltage values closer together. But I have yet to conclusively prove this to be the case.

CPUZ Validation



Click image for full screenshot


Super Pi 32M and Everest Bandwidth results

As you can see with loose Static tRead value of 10, Everest bandwidth and latency is slow and Super Pi 32M time is ~15 to 20 seconds slower than what is should be but not bad for low MCH voltage of 1.42v

Click image for full screenshot





Bios settings used:
Code:
GIGABYTE GA-EP45_EXTREME
MB Intelligent Tweaker(M.I.T.)
Robust Graphics Booster:  AUTO
CPU Clock Ratio: 8x
Fine CPU Clock Ratio: [+0.0]
CPU Frequency: 4000Mhz

Clock Chip Control 
Standard Clock Control
CPU Host Clock Control: [Enabled]
CPU Host Frequency(Mhz): 500 Mhz
PCI Express Frequency(Mhz): 100 Mhz
C.I.A. 2: [Disabled]

Advanced Clock Control [Press Enter]
CPU Clock Drive: 800mv
PCI Express Clock Drive: 800mv
CPU Clock Skew: 200ps
MCH Clock Skew: 200ps

DRAM Performance Control
Performance Enhance: [Standard]
Extreme Memory Profile (X.M.P.): Disabled
(G)MCH Frequency Latch: [Auto]
System Memory Multiplier: 2.4B
Memory Frequency (Mhz): 1200Mhz
DRAM Timing Selectable: [Manual]
Standard Timing Control
CAS Latency Time: 5
tRCD: 5
tRP:  5
tRAS: 15

Advanced Timing Control [Press Enter]
tRRD: 4
tWTR: 8
tWR: 10
tRFC: 42
tRTP: 4
Command Rate (CMD): AUTO

Channel A
Static tRead Value: 10
tRD Phase0 Adjustment: 1-Advanced
tRD Phase1 Adjustment: Auto
tRD Phase2 Adjustment: 1-Advanced
tRD Phase3 Adjustment: 1-Advanced
Trd2rd(Different Rank).: Auto 
Twr2wr(Different Rank): Auto 
Twr2rd(Different Rank): Auto 
Trd2wr(Same/Diff Rank): Auto 
Dimm1 Clock Skew Control: Auto  ps
Dimm2 Clock Skew Control: Auto  ps

Channel B
Static tRead Value: 10
tRD Phase0 Adjustment: 0-Normal
tRD Phase1 Adjustment: 0-Normal
tRD Phase2 Adjustment: 0-Normal
tRD Phase3 Adjustment: 0-Normal
Trd2rd(Different Rank).: Auto 
Twr2wr(Different Rank): Auto 
Twr2rd(Different Rank): Auto 
Trd2wr(Same/Diff Rank): Auto 
Dimm1 Clock Skew Control: Auto  ps
Dimm2 Clock Skew Control: Auto  ps

Motherboard Voltage Control

CPU Vcore: 1.3000v
CPU Termination | 1.200V: 1.3000v
CPU PLL | 1.500V: 1.500v
CPU Reference | 0.760V: 0.826v
CPU Reference2 | 0.800V: 0.843v

MCH Core | 1.100V: 1.42v
MCH Reference | 0.800V: 0.803v
MCH/DRAM Ref | 0.900V: AUTO v
ICH I/O | 1.500V: AUTO v
ICH Core | 1.100V: AUTO v

DRAM Voltage | 1.800V: 2.280v
DRAM Termination | 0.900V: AUTO v
Channel A Reference | 0.900V: AUTO v
Channel B Reference | 0.900V: AUTO v

Advanced Bios Features
Limit CPUID Max. to 3: [Disabled]
No-Execute Memory Protect: [Disabled]
CPU Enhanced Halt (C1E): [Disabled]
C2/C2E State Support: [Disabled]
x C4/C4E State Support: [Disabled]
CPU Thermal Monitor 2(TM2): [Disabled]
CPU EIST Function: [Disabled]
Virtualization Technology.: [Disabled]

Last edited by eva2000; 13-08-2008 at 03:06 AM.
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Old 29-07-2008, 06:49 AM   #3 (permalink)
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EP45 Extreme MCH tweaking

EP45 Extreme MCH tweaking

So far with F6a bios, I haven't been able to get as much clock for clock performance out of the system as the P45 chipset seems to not like very high MCH northbridge voltage above 1.42-1.5v. So I thought I'd check to see if there's any MCH tweaks to squeeze out more performance without needing too high MCH/NB volts similar to the Asus P5B Deluxe/Commando JP Strap tweaks.

To do this, I started with the base overclock at 9x445FSB 2.0B divider 445Mhz 5-5-5-15 memory clocks with subtimings set on AUTO and Performance Enhance set to Standard. Turbo had a bit of gain in Copy bandwidth though. I then compared them with changes in only static tRead from AUTO vs 10 vs 9 and with changes in windows using memset for tREF and Pmem or Super Pi Tweaker 1.04v MCH editing tab for FED1403F address.

I used Everest Ultimate 4.50.1469 memory bandwidth test to compare the changes.

Configurations tested:
  1. 4005Mhz - 9x445FSB 1:1 445Mhz 5-5-5-15 Performance Enhanced = Standard | Static tRead: Auto (vNB = 1.30v)
  2. 4005Mhz - 9x445FSB 1:1 445Mhz 5-5-5-15 Performance Enhanced = Turbo | Static tRead: Auto (vNB = 1.30v)
  3. 4005Mhz - 9x445FSB 1:1 445Mhz 5-5-5-15 Performance Enhanced = Standard | Static tRead: 10 (vNB = 1.30v)
  4. 4005Mhz - 9x445FSB 1:1 445Mhz 5-5-5-15 Performance Enhanced = Standard | Static tRead: 10 Tweak 1 (vNB = 1.30v)
  5. 4005Mhz - 9x445FSB 1:1 445Mhz 5-5-5-15 Performance Enhanced = Standard | Static tRead: 9 (vNB = 1.40v)
  6. 4005Mhz - 9x445FSB 1:1 445Mhz 5-5-5-15 Performance Enhanced = Standard | Static tRead: 9 Tweak 1 (vNB = 1.40v)
  7. 4005Mhz - 9x445FSB 1:1 445Mhz 5-5-5-15 Performance Enhanced = Standard | Static tRead: 9 Tweak 1 + 2 (vNB = 1.40v)
  8. 8x500FSB 2.40B 5:6 5-5-5-15 Std tRead = 10 (vNB = 1.42v)
  9. 8x500FSB 2.40B 5:6 5-5-5-15 Turbo tRead = 9 (vNB = 1.50v)
  10. 8x500FSB 2.40B 5:6 5-5-5-15 Turbo tRead = 9 Tweak 1 (vNB = 1.50v)
  11. 8x500FSB 2.40B 5:6 5-5-5-15 Turbo tRead = 9 Tweak 1+2 (vNB = 1.50v)

Click image for full results including L1 and L2 cache bandwidth and latencies.






Notes:
  • Tweak 1 = FED1403F MCH address change from 65 to 60
  • Tweak 2 = Memset change tREF to 16383T
  • tRead of 9 and tighter needed vNB of 1.40v to boot
  • The tRead phase 0 to 3 adjustments couldn't be advanced on any channels at tRead 10 with just 1.30v NB volts

The result is some success I think as you can see the static tRead 10 + Tweak 1 required only 1.30v NB volts to get similar performance as static tRead 9 which required 1.40v NB volts. More testing is needed at even higher FSB and tighter timings though.

9x445FSB 1:1 5-5-5-15

tRead AUTO (left) & 10 (right)


tRead 10 + Tweak 1 (left) & 9 (right)


tRead 9 + Tweak 1 (left) & 9 + Tweak 1 + 2 (right)


8x500FSB 5:6 5-5-5-15

tRead 9 + Tweak 1 + 2



Super Pi 32M v1.50

9x445FSB 1:1 5-5-5-15

tRead 10 = 12min 20.843s
vs
tRead 9 Tweak 1+2 = 12min 09.859s

8x500FSB 5:6 5-5-5-15

tRead 10 = 11min 44.141s
vs
tRead 9 Tweak 1+2 = 11min 34.563s



Bios settings used for 9x445FSB 1:1 :
Code:
GIGABYTE GA-EP45_EXTREME
MB Intelligent Tweaker(M.I.T.)
Robust Graphics Booster:  AUTO
CPU Clock Ratio: 9x
Fine CPU Clock Ratio: [+0.0]
CPU Frequency: Mhz: 4.00Ghz

Clock Chip Control 
Standard Clock Control
CPU Host Clock Control: [Enabled]
CPU Host Frequency(Mhz): 445 Mhz
PCI Express Frequency(Mhz): 100 Mhz
C.I.A. 2: [Disabled]

Advanced Clock Control [Press Enter]
CPU Clock Drive: 800mv
PCI Express Clock Drive: 700mv
CPU Clock Skew: 0ps
MCH Clock Skew: 0ps

DRAM Performance Control
Performance Enhance: [Standard]
Extreme Memory Profile (X.M.P.): Disabled 
(G)MCH Frequency Latch: [Auto]
System Memory Multiplier: 2.0B
Memory Frequency (Mhz): 890Mhz
DRAM Timing Selectable: [Manual]
Standard Timing Control
CAS Latency Time: 5
tRCD: 5
tRP:  5
tRAS: 15 

Advanced Timing Control [Press Enter]
tRRD: AUTO
tWTR: AUTO
tWR: AUTO
tRFC: AUTO
tRTP: AUTO
Command Rate (CMD): AUTO

Channel A
Static tRead Value: AUTO vs 10 vs 9
tRD Phase0 Adjustment: Auto
tRD Phase1 Adjustment: Auto
tRD Phase2 Adjustment: Auto
tRD Phase3 Adjustment: Auto
Trd2rd(Different Rank).: Auto 
Twr2wr(Different Rank): Auto 
Twr2rd(Different Rank): Auto 
Trd2wr(Same/Diff Rank): Auto 
Dimm1 Clock Skew Control: Auto  ps
Dimm2 Clock Skew Control: Auto  ps

Channel B
Static tRead Value: Auto vs 10 vs 9

tRD Phase0 Adjustment: Auto
tRD Phase1 Adjustment: Auto
tRD Phase2 Adjustment: Auto
tRD Phase3 Adjustment: Auto
Trd2rd(Different Rank).: Auto 
Twr2wr(Different Rank): Auto 
Twr2rd(Different Rank): Auto 
Trd2wr(Same/Diff Rank): Auto 
Dimm1 Clock Skew Control: Auto  ps
Dimm2 Clock Skew Control: Auto  ps

Motherboard Voltage Control

CPU Vcore: 1.300v
CPU Termination | 1.200V: 1.240v
CPU PLL | 1.500V: 1.500 v
CPU Reference | 0.760V: 0.786v
CPU Reference2 | 0.800V: 0.805v

MCH Core | 1.100V: 1.300v (tRead AUTO and 10) vs 1.400v (tRead 9)
MCH Reference | 0.800V: 0.765v
MCH/DRAM Ref | 0.900V: AUTO v
ICH I/O | 1.500V: AUTO v
ICH Core | 1.100V: AUTO v

DRAM Voltage | 1.800V: 2.000v / 2.100v
DRAM Termination | 0.900V: AUTO v
Channel A Reference | 0.900V: AUTO v
Channel B Reference | 0.900V: AUTOv



[b]Advanced Bios Features[b]
Limit CPUID Max. to 3: [Disabled]
No-Execute Memory Protect: [Disabled]
CPU Enhanced Halt (C1E): [Disabled]
C2/C2E State Support: [Disabled]
x C4/C4E State Support: [Disabled]
CPU Thermal Monitor 2(TM2): [Disabled]
CPU EIST Function: [Disabled]
Virtualization Technology.: [Disabled]

Last edited by eva2000; 13-08-2008 at 04:35 AM.
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Old 29-07-2008, 06:49 AM   #4 (permalink)
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5:6 Memory Divider (2.40B) + MCH Tweak Testing

5:6 Memory Divider (2.40B) + MCH Tweak Testing

Revisiting the 2.40B 5:6 memory divider but this time I've gotten a better handle on tweaking memory, voltages and the above outlined MCH tweaks

I had no problems using NB (MCH) voltage of 1.56v for these tests which helped stablise the high 640Mhz 5-5-5-15 memory clock along with what P45 chipset considers tight tRead value of 9.

Setting the 4 subtimings listed here to the following also helped stablise memory clock at 640mhz 5-5-5-15 at 2.56v
  • Trd2rd(Different Rank).: 10
  • Twr2wr(Different Rank): 9
  • Twr2rd(Different Rank): 9
  • Trd2wr(Same/Diff Rank): 10

7.5x533FSB 2.40B 640Mhz 5-5-5-15






tRD 9


tRD 9 + Tweak 1


tRD 9 + Tweak 1 + 2


Super Pi 1M with Tweak 1 + 2


Super Pi 32M with Tweak 1 + 2


32M time still around 20-25 seconds slower than P35/X38/X48 but getting there

Last edited by eva2000; 13-08-2008 at 03:05 AM.
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Old 29-07-2008, 06:49 AM   #5 (permalink)
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Gigabyte GA-EP45 Extreme F6c bios released

F6c bios released

The EP45 Extreme is getting better - just received F6c bios and my max FSB with E8500 jumped from 560FSB to 600FSB so far with not many changes in bios.

I'm actually fairly confident if this F6c bios can give me the FSB, I can match the biostar for clock for clock performance

4400Mhz at 1.424v idle / 1.396v load
- 8x550FSB 2.0B 4-4-4-12


Seems still can't get 600FSB windows stable but memtest and bootable is okay. Just playing around with high cpu clock and 8x550FSB 2.0B 4-4-4-12 is wprime v1.62 stable but can't run single Super Pi 32M - probably because wprime tests cpu more and Super Pi tests memory. So need to work out the memory settings.

tRD 9 & tRD 9 + Tweak 1 & tRD 9 + Tweak 1 + 2


wPrime v1.62 32M & 1024M


Update: looks like F6c improved memory read bandwidth with same settings as now I can't implement tRead of 9 and the 2 MCH tweaks (1 + 2) at same settings and volts without windows freezing. So I have to use tRead of 10 and if I bump up vdimm and MCH/NB volts i can apply the 2 MCH tweaks and run everest and super pi 1-8m, but can't get it 32M stable with the manual MCH tweaks.

So here's a 8x550FSB 2.0B 5-5-5-15 run

click image for full screenshot and everest bandwidth results



Still around 35-40 seconds slower than P35/X38/X48 I estimate but getting there.

Last edited by eva2000; 14-08-2008 at 11:22 PM.
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Old 29-07-2008, 06:49 AM   #6 (permalink)
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F6K bios released for EP45 Extreme

F6K Bios Released

Gigabyte has released F6K bios with better memory oc'ing support it seems http://www.giga-byte.com/Support/Mot...ProductID=2860. Just flashed to F6K and will test with this memory that arrived 2x1GB Team PC2-10400 C6



here's F6K bios template, with addition of a new option called DDR3 Write training (this is a DDR2 board typo ? )

F6K Bios Template
Code:
GIGABYTE GA-EP45_EXTREME
MB Intelligent Tweaker(M.I.T.)
Robust Graphics Booster:  AUTO
CPU Clock Ratio: 9x
Fine CPU Clock Ratio: [+0.5]
CPU Frequency: Mhz

Clock Chip Control 
Standard Clock Control
CPU Host Clock Control: [Enabled]
CPU Host Frequency(Mhz): 333 Mhz
PCI Express Frequency(Mhz): 100 Mhz
C.I.A. 2: [Disabled]

Advanced Clock Control [Press Enter]
CPU Clock Drive: mv
PCI Express Clock Drive: mv
CPU Clock Skew: ps
MCH Clock Skew: ps

DRAM Performance Control
Performance Enhance: [Turbo]
Extreme Memory Profile (X.M.P.): 
(G)MCH Frequency Latch: [Auto]
System Memory Multiplier:
Memory Frequency (Mhz): Mhz
DRAM Timing Selectable: [Manual]
Standard Timing Control
CAS Latency Time: 
tRCD: 
tRP:  
tRAS:  

Advanced Timing Control [Press Enter]
tRRD:
tWTR:
tWR:
tRFC:
tRTP:
Command Rate (CMD):

>>>>> Channel A
Channel A Timing Settings: [Press Enter]
Static tRead Value: Auto
tRD Phase0 Adjustment: Auto
tRD Phase1 Adjustment: Auto
tRD Phase2 Adjustment: Auto
tRD Phase3 Adjustment: Auto
Trd2rd(Different Rank).: Auto 
Twr2wr(Different Rank): Auto 
Twr2rd(Different Rank): Auto 
Trd2wr(Same/Diff Rank): Auto 
Dimm1 Clock Skew Control: Auto  ps
Dimm2 Clock Skew Control: Auto  ps
DDR3 Write Training: Auto/Enabled/Disabled

Channel A Driving Settings: [Press Enter]
Driving Strength Profile: AUTO/667Mhz/800Mhz/1066Mhz/OC-1200/OC-1333

Data Driving Pull-Up Level: AUTO
Cmd Driving Pull-Up Level: AUTO
Ctrl Driving Pull-Up Level: AUTO
Clk Driving Pull-Up Level: AUTO

Data Driving Pull-Down Level: AUTO
Cmd Driving Pull-Down Level: AUTO
Ctrl Driving Pull-Down Level: AUTO
Clk Driving Pull-Down Level: AUTO

>>>>> Channel B
Channel B Timing Settings: [Press Enter]
Static tRead Value: Auto
tRD Phase0 Adjustment: Auto
tRD Phase1 Adjustment: Auto
tRD Phase2 Adjustment: Auto
tRD Phase3 Adjustment: Auto
Trd2rd(Different Rank).: Auto 
Twr2wr(Different Rank): Auto 
Twr2rd(Different Rank): Auto 
Trd2wr(Same/Diff Rank): Auto 
Dimm1 Clock Skew Control: Auto  ps
Dimm2 Clock Skew Control: Auto  ps
DDR3 Write Training: Auto/Enabled/Disabled

Channel B Driving Settings: [Press Enter]
Driving Strength Profile: AUTO/667Mhz/800Mhz/1066Mhz/OC-1200/OC-1333

Data Driving Pull-Up Level: AUTO
Cmd Driving Pull-Up Level: AUTO
Ctrl Driving Pull-Up Level: AUTO
Clk Driving Pull-Up Level: AUTO

Data Driving Pull-Down Level: AUTO
Cmd Driving Pull-Down Level: AUTO
Ctrl Driving Pull-Down Level: AUTO
Clk Driving Pull-Down Level: AUTO

Motherboard Voltage Control

CPU Vcore: v
CPU Termination | 1.200V: v
CPU PLL | 1.500V: v
CPU Reference | 0.760V: v
CPU Reference2 | 0.800V: v

MCH Core | 1.100V: v
MCH Reference | 0.800V: v
MCH/DRAM Ref | 0.900V: v
ICH I/O | 1.500V: v
ICH Core | 1.100V: v

DRAM Voltage | 1.800V: v
DRAM Termination | 0.900V: v
Channel A Reference | 0.900V: v
Channel B Reference | 0.900V: v

Advanced Bios Features
Limit CPUID Max. to 3: [Disabled]
No-Execute Memory Protect: [Disabled]
CPU Enhanced Halt (C1E): [Disabled]
C2/C2E State Support: [Disabled]
x C4/C4E State Support: [Disabled]
CPU Thermal Monitor 2(TM2): [Disabled]
CPU EIST Function: [Disabled]
Virtualization Technology.: [Disabled]

Integrated Peripherals
SATA RAID/AHCI Mode: [Disabled]
SATA Port0-3 Native Mode: [Disabled]
USB Controller: [Enabled]
USB 2.0 Controller: [Enabled]
USB Keyboard Support: [Disabled]
USB Mouse Support: [Disabled]
Legacy USB storage detect: [Enabled]
654Mhz - 666Mhz 5-5-5-15 at 2.58v bios set

F6K bios seems to be about same as F6H just slightly better as I couldn't get to stable 7.5x534FSB 2.4B 640Mhz 5-5-5-15 on F6H like I did on F6A with these Team PC2-10400 memories. Clock for clock performance is still not where I want it to be for Super Pi, but getting better with each bios release


[Click thumbnail to view full size photo
- use keyboard arrow keys to cycle through images
- click and hold full size photo to drag and move around]


@666Mhz 5-5-5-15 at 2.58v Everest only


@654Mhz 5-5-5-15 at 2.58v - Single & Dual Super Pi 32M stable

Single 32M (left) & Dual 32M via HyperPi (right)


Bios settings used:
Code:
GIGABYTE GA-EP45_EXTREME
MB Intelligent Tweaker(M.I.T.)
Robust Graphics Booster:  AUTO
CPU Clock Ratio: 7x
Fine CPU Clock Ratio: [+0.5]
CPU Frequency: 4087Mhz

Clock Chip Control 
Standard Clock Control 
CPU Host Clock Control: [Enabled]
CPU Host Frequency(Mhz): 545 Mhz
PCI Express Frequency(Mhz): 100 Mhz
C.I.A. 2: [Disabled]

Advanced Clock Control [Press Enter]
CPU Clock Drive: 800mv
PCI Express Clock Drive: 900mv
CPU Clock Skew: 100ps
MCH Clock Skew: 50ps

DRAM Performance Control
Performance Enhance: [Turbo]
Extreme Memory Profile (X.M.P.): Disabled
(G)MCH Frequency Latch: [Auto]
System Memory Multiplier: 2.4B
Memory Frequency (Mhz): 1308Mhz
DRAM Timing Selectable: [Manual]
Standard Timing Control
CAS Latency Time: 5
tRCD: 5
tRP: 5
tRAS: 15

Advanced Timing Control [Press Enter]
tRRD: 5
tWTR: 5
tWR: 13
tRFC: 52
tRTP: 5
Command Rate (CMD): AUTO

>>>>> Channel A
Channel A Timing Settings: [Press Enter]
Static tRead Value: 10
tRD Phase0 Adjustment: Auto
tRD Phase1 Adjustment: Auto
tRD Phase2 Adjustment: Auto
tRD Phase3 Adjustment: Auto
Trd2rd(Different Rank).: Auto 
Twr2wr(Different Rank): Auto 
Twr2rd(Different Rank): Auto 
Trd2wr(Same/Diff Rank): Auto 
Dimm1 Clock Skew Control: Auto  ps
Dimm2 Clock Skew Control: Auto  ps
DDR3 Write Training: Auto

Channel A Driving Settings: [Press Enter]
Driving Strength Profile: AUTO

Data Driving Pull-Up Level: AUTO
Cmd Driving Pull-Up Level: AUTO
Ctrl Driving Pull-Up Level: AUTO
Clk Driving Pull-Up Level: AUTO

Data Driving Pull-Down Level: AUTO
Cmd Driving Pull-Down Level: AUTO
Ctrl Driving Pull-Down Level: AUTO
Clk Driving Pull-Down Level: AUTO

>>>>> Channel B
Channel B Timing Settings: [Press Enter]
Static tRead Value: 10
tRD Phase0 Adjustment: Auto
tRD Phase1 Adjustment: Auto
tRD Phase2 Adjustment: Auto
tRD Phase3 Adjustment: Auto
Trd2rd(Different Rank).: Auto 
Twr2wr(Different Rank): Auto 
Twr2rd(Different Rank): Auto 
Trd2wr(Same/Diff Rank): Auto 
Dimm1 Clock Skew Control: Auto  ps
Dimm2 Clock Skew Control: Auto  ps
DDR3 Write Training: Auto/Enabled/Disabled

Channel B Driving Settings: [Press Enter]
Driving Strength Profile: AUTO

Data Driving Pull-Up Level: AUTO
Cmd Driving Pull-Up Level: AUTO
Ctrl Driving Pull-Up Level: AUTO
Clk Driving Pull-Up Level: AUTO

Data Driving Pull-Down Level: AUTO
Cmd Driving Pull-Down Level: AUTO
Ctrl Driving Pull-Down Level: AUTO
Clk Driving Pull-Down Level: AUTO

Motherboard Voltage Control

CPU Vcore: 1.2500v
CPU Termination | 1.200V: 1.360v
CPU PLL | 1.500V: 1.500v
CPU Reference | 0.760V: 0.866v
CPU Reference2 | 0.800V: 0.881v

MCH Core | 1.100V: 1.600v
MCH Reference | 0.800V: 0.841v
MCH/DRAM Ref | 0.900V: AUTOv
ICH I/O | 1.500V: 1.56v
ICH Core | 1.100V: 1.16v

DRAM Voltage | 1.800V: 2.58v
DRAM Termination | 0.900V: AUTOv
Channel A Reference | 0.900V: AUTOv
Channel B Reference | 0.900V: AUTOv

Advanced Bios Features
Limit CPUID Max. to 3: [Disabled]
No-Execute Memory Protect: [Disabled]
CPU Enhanced Halt (C1E): [Disabled]
C2/C2E State Support: [Disabled]
x C4/C4E State Support: [Disabled]
CPU Thermal Monitor 2(TM2): [Disabled]
CPU EIST Function: [Disabled]
Virtualization Technology.: [Disabled]

Integrated Peripherals
SATA RAID/AHCI Mode: [Disabled]
SATA Port0-3 Native Mode: [Disabled]
USB Controller: [Enabled]
USB 2.0 Controller: [Enabled]
USB Keyboard Support: [Disabled]
USB Mouse Support: [Disabled]
Legacy USB storage detect: [Enabled]

Last edited by eva2000; 28-08-2008 at 01:02 AM.
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Old 02-08-2008, 01:58 PM   #7 (permalink)
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Re: Gigabyte GA-EP45 Extreme rev1.0 Review

eva2000, does your analysis of this board consider it ok for high stable overclocks?
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Old 02-08-2008, 09:16 PM   #8 (permalink)
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Re: Gigabyte GA-EP45 Extreme rev1.0 Review

FWIW: you may wish to compare your initial impressions with ocwb (but F5E bios)
http://my.ocworkbench.com/2008/gigab...Extreme/g1.htm

Note: There is no review pages "menu", so you have to keep hitting "next" at bottom left
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