raja

Channel 2 & Channel 3 will be + addtional clock skew due to distance from CPU. So, if slot 1 is @ 540 ps at X freq, then slot 2 & 3 maybe +100~300ps extra.

Switching frequency is to adjust transient response of rail, quicker error recovery when faced with load change.

SAE

Wow, that's quite some heavy stuff to digest, Raju! Seems it's enough to scratch the surface of it to perform well.
I cannot imagine how I could assimilate such a knowlegde without an engineering background... I'll have a look at this xls of yours later, thanks again mate for shedding some light on this.

Cyb3rGlitch

Awesome! This is the stuff that I've been eager to learn about. Cheers!

raja

[quote=raja;122660]Channel 2 & Channel 3 will be + addtional clock skew due to distance from CPU. So, if slot 1 is @ 540 ps at X freq, then slot 2 & 3 maybe +100~300ps extra.

quote]


I should correct this to say - this really depends on how well the traces are matched in length. The traces to the closest slots should be snaked back on themsleves to add length so that they may use the same level of skew as the further slots (this is board dependant). On some boards you can run the same RTL to both channels if the trace length is well matched.

later
Raja

eva2000

Yeah i find both DFI UT X58 and Asus P6T6 WS Revolution occasionally have RTL B/C channels with same RTL values at certain clocks without problems.

raja

Sounds about right. At certain frequncies, parasitic capacitance and inductance may start to play a part in the required level of skew. There's also the possibility of varaince between the transmiter stages and their slew rate for a given rail voltage and how well they drive into a capacitive load. All of this can add up to change the level of skew sensed by the IMC during post.

later
Raja

eva2000

I'm also finding on Asus P6T6 WS Revolution that certain memory modules i.e. 6GB Gskill Trident 2000C9, if I set DDRAM Data/CTRL VREF to 0.480/0.480 on channel C I can clock the memory more stably especially for 8x32M Pi Hyper Pi runs.

Running 6x 2GB A-Data 2000X on same board also resulted in weird optimal DATA/CTRL VREF for A/B/C channels too of 0.480/0.525/0.470 for both DATA and CTRL A/B/C channels 12GB A-DATA 2000X DDR3 testing - although once set 6x2GB @DDR3-2000Mhz 8-9-8-x 2T was pretty easy at 1.62v

Would love to see Anandtech do something to cover DATA/CTRL VREF for the layman among us

raja

Most of it is identical to GTL reference voltage tuning, refer to work by Kris (on TTR) or by John (on edge of stability). The general concept is identical, especialy for CMD/ADDR reference. The DQ line is differential, so the reference point is set at the midpoint (50%) by default.