Round Trip Latency’ chipset function in BIOS denotes the number of Uncore Clock cycles that pass before data arrives back at the IMC after a read command is issued...


Manual control of the RTL function has been added by board vendors to P55/X58, primarily to allow looser manual settings or to lock the setting down to a known working value. The latter is required at times because there are instances where the IMC selects a non-ideal/unstable setting for one of the memory channels, in which case locking these values down to a stable setting prevents random crashes and bizarre system instability between system reboots. Changes of 1-2 clocks below the auto-selected RTL value are sometimes possible for light load benchmarks such as a single thread of Super Pi 32M thus giving a small boost in the final time.

Socket 1156 CPU’s have their Uncore frequency multiplier locked, so there’s not too much to look out for other than a quick glance at the real RTL time in nanoseconds, to make sure that the clock crossing schedule is just as fast if not faster than your previous selected overclock.

For those of you playing around with socket 1366 processors, you get some control over the Uncore multiplier ratio (so long as you observe the minimum 2x memory multiplier rule). Bear in mind that as you increase the Uncore frequency, the RTL value will increase because more clock cycles pass over the same time period.

Any greater than 13.57ns, and we have lost system performance and as a double whammy will also have to increase memory controller voltage to facilitate the higher switching speed of the associated IMC stages; this is not the way to truly ‘overclock’ a system for better performance.

certain ranges for RTL for particular timing/frequencies

Raj posted a whole article on these RTL and http://www.anandtech.com/show/2869/6



So

Read time in nanoseconds = RTL x 1000/Uncore frequency

RTL = 54 with Uncore = 4000mhz and cas8 and tRCD8 means:

read time = 54 x 1000/4000 = 13.5ns

if bump uncore to 21x multi, RTL value should move out to ~57:

57 x 1000/4200 = 13.57ns



But they have a more updated formula

A few more questions conerning RTL:
1. It seems that MBs change RTL(Auto) with Vtt, why?
2. Do MBs change RTL(Auto) and other sub-timings with specific RAM(e.g. spd) / CPU?
3. RTL for Channel A is easier to figure out, and MBs usually set it good.
What is the typcial RTL for Channel B/Channel C?
It seems that MBs are not very consistent on RTL B/C.

Any typical RTL_B/RTL_C values for CL6/CL7/CL8?

4. I thought that RTL_A/RTL_B/RTL_C absolute values are critical(and directly used), while (RTL_B-RTL_A)/(RTL_C-RTL_B) values are useless(never referenced in such way). Is it correct?
e.g. For a specific ram settings, if RTL 49/51/53 works, does 50/51/53 always work? Or only 50/52/54 is guaranteed to work?

1) At higher DRAM frequencies there may be some drift in clock skew sensing (better known as read and write levelling). Changes in VTT facilitate a change in slew rate (the speed at which voltage increases/changes or is amplified) - this can change required clocks skews and in some instances create situations where the command or data lines are unstable during POST.

2) The CPU clock freqeuncy has no part in the Round Trip Latency value per se. The Uncore (memory controller frequency), tCL (CAS) and clock skew between the Uncore and DRAM do.

3) No typical values per se, although most of the time the memory controller prefers channel B and C to be offset by a few clocks past A. So channel B is generally +2~3 clocks and Channel C +3~5 clocks over the Channel A value. Assuming trace lengths are well matched between slots the need for such offset lies within the memory controller (although capacitance of serpentine traces may come into play at higher frequency).

4) There is a margin of pad open time - the IMC receiver stages have to be available for the transaction. The value does not have to be absolute, it depends on the size of the buffer stack. Too tight or too loose, either can cause invalid timing because when the DRAM IO buffers burst the data there will be no available agent ready to receive it (the data cannot be held in the traces between the DRAM and Uncore).


Later
Raja