Originally Posted by cstkl1

make it easy

bios set 1-7 , tRRD is 1-7 tWRWR =4
bios set 8-15, tRRD is 0-7 tWRWR =6

default is
bios set 6, tRRD is 6, tWRWR = 4
so if we want to change only tWRWR to 6 only
we need to change bios set to 14. to get tRRD 6, tWRWR 6


the bios doesnt allot tRRD 0 tWRWR 4
eventhough intel spec sheet said its possible.

Originally Posted by cstkl1

random pagefile error
and when hang u will seee the razer battlelight still on and a few other lights but the main backlight will go off .. even mouse etc

eva just got 201mhz stable at 1n 2000mhz cl7 but dram at 1.66 but this is the freakish part

i realized my mobo likes ioh/ich to ioh analogue to be this ratio for set
1.08set/1.1set or 1.21set/1.20set and 1.31set/1.3set.

so for
2000mhz CL7 1n i need 1.31set/1.3set with vdimm 1.680set ( read 1.66)
for 2000mhz CL7 2n i need 1.21set/1.2set with vdimm 1.665( read 1.64)

i still think for ram timings is the mobo and nothing to do with proc.
so i guess my mobo just suck.. but good enough

for the full stability also depended on one more setting only which influenced the proc imc setting
testing that fully now before i post that assumption
but found this thing that felix mentioned

Code:

bios     bits9    876
tRRD     tWRWR    tRRD
 0         0       000      
 1         0       001      
 2         0       010      
 3         0       011      
 4         0       100      
 5         0       101      
 6         0       110      
 7         0       111      
 8         1       000      
 9         1       001      
10         1       010     
11         1       011     
12         1       100    
13         1       101    
14         1       110    
15         1       111

so u can see setting the bios in DFI tRRD is 0-7. and tWRWR is either 4 or 6
so setting 1-7 tWRWR is 4 , 8 ( is actually 0) -15 ( actually 7) tWRWR is 6.

found this interesting
not sure how relevant.
wonder how many other bios setting works this way.

so try setting 14/15 .. get more consistent result with tWRWR at 6.
this part i guess is cpu since tWRWR is IMC .

Originally Posted by cstkl1

eva is it possible to request dfi engineer
to make the rtl setting adjustable for channel A, B and C

i think the 1n issue is because of the C is only +1 to B

in r2e C must be min +2-3 of B

the problem is only for 1n hyperpi 32m inconsistency 16 threads is impossible atm. for 201 bclk 2010 mhz Cl7 1n
prime95 and linx doesnt seem to be fussy about it.