DFI P35-T2R Overclocking etc..

rlm · 27-08-2007, 03:45 AM

Just thought I'd start a general thread.

- Channel 1 CLK fine delay: CURRENT [13]
- Channel 2 CLK fine delay: CURRENT [12]

These 2 are most tricky to get right so play with their values to see if it improves or makes worse your oc's

Seems these values change significantly with different dividers. So for instance on a 266/667 the values on mine are around 12-14. With the 266/800 around 1-3.

The most impact from changing these values I've seen so far is with the 266/800 divider. Loosening them up a bit let's me hit higher mhz with my ram.

Swapped out the Gskill for Geil 8500 cas 4's. Have been able to boot up at 1248 mhz 5-5-5-15. I couldn't do this with the ip35 pro, topping out at about 1140 ish. So happy about that.

No performance increase over 1040mhz 4-4-4-12 in superpi 1m, but an interesting development for me

Note not tested for any real stability.

CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Enabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 9x
- Target CPU Clock: 3735
CPU Clock:415
Boot Up Clock:auto
DRAM Speed:266/800
- Target DRAM Speed:1248
PCIE Clock: 100mhz

Voltage Settings
CPU VID Control:1.5 (1.52 SMG 1.5 Full Load)
CPU VID Special Add: Auto
DRAM Voltage Control: 2.47 volts (2.43v in SMG)
SB 1.05V Voltage: 1.15v
SB Core/CPU PLL Voltage: 1.75v
NB Core Voltage:1.5 v
CPU VTT Voltage: 1.53v
Vcore Droop Control: Disabled (Does the opposite??)
Clockgen Voltage Control: 3.6 v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Enabled
x CPU GTL1/3 REF Volt: 100
x CPU GTL 0/2 REF Volt: 100
x North Bridge GTL REF Volt: 105

DRAM Timing
- Enhance Data transmitting: Auto
- Enhance Addressing: Auto
- Channel 1 CLK fine delay: 4
- Channel 2 CLK fine delay: 4

CAS Latency Time (tCL): 5
RAS# to CAS# Delay (tRCD): 5
RAS# Precharge (tRP): 5
Precharge Delay (tRAS): 15
All Precharge to Act: AUTO (5)
REF to ACT Delay (tRFC): AUTO (42)
Performance Level: AUTO (5)
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO (14)
Rank Write to Read (tWTR): AUTO (11)
ACT to ACT Delay (tRRD): AUTO (3)
Read to Write Delay (tRDWR): AUTO (8)
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO (3)
ALL PRE to Refresh: AUTO (5)

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Cheers

RLM

ncsa · 27-08-2007, 08:35 PM

BIOS 0810
Default Settings with vDimm bumped to 2.0 and C4-4-4-12
FSB 333

Code:

CPU Feature
- Thermal Management Control: Enabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Enabled
- Virtualization Technology: Enabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 9
- Target CPU Clock: 3000
CPU Clock: 333
Boot Up Clock: Auto
DRAM Speed: 333/800
- Target DRAM Speed: 800
PCIE Clock: 100mhz

Voltage Settings
CPU VID Control: AUTO
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.000
SB 1.05V Voltage: 1.070
SB Core/CPU PLL Voltage: 1.55
NB Core Voltage: 1.33
CPU VTT Voltage: 1.20
Vcore Droop Control: Enabled (= Disabled)
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: AUTO
- Enhance Addressing: AUTO
- Channel 1 CLK fine delay: AUTO (Current[2])
- Channel 2 CLK fine delay: AUTO (Current [2])

CAS Latency Time (tCL): 4
RAS# to CAS# Delay (tRCD): 4
RAS# Precharge (tRP): 4
Precharge Delay (tRAS): 12
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance Level: AUTO
Read delay phase adjust: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

FSB 6x480 but as we all know a CPUz shot means nothing without some real tests beside it

eva2000 · 27-08-2007, 09:13 PM

Nice RLM and ncsa...

Yes CLK fine delay is tricky....

Just received 8/23 bios as well change log

http://fileshosts.com/intel/DFI/DFI_...a/LP35D823.zip

8/23 bios

1. "added ALC888 SSID.
2. Modifying "" CPU VID Special Add"" percentage table "
3. Fixed can't boot from sata cdrom when enable raid. We have change the ICH9 AHCI and RAID BIOS initial method to fix RAID building issue

Have yet to try it

ncsa · 27-08-2007, 09:26 PM

Thanks eva ... hopefully the RAID changes does not change its performance ... will compare later..

ncsa · 28-08-2007, 03:57 PM

BIOS 0823

Changes in BIOS
Intergrated Peripherals -> OnChip IDE Device -> Run AHCI ROM -Enabled (Default)

Intergrated DIsplay First - OnBoard

DRAM Timings - CLK Fine Delay now available across individual DIMM slots

Vcore Droop Control: Enabled (Default) - Set to Disabled to activate this feature

Use list below for sharing 0823 BIOS settings

Code:

CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio:
- Target CPU Clock:
CPU Clock:
Boot Up Clock:
DRAM Speed:
- Target DRAM Speed:
PCIE Clock: 100mhz

Voltage Settings
CPU VID Control:
CPU VID Special Add:
DRAM Voltage Control:
SB 1.05V Voltage:
SB Core/CPU PLL Voltage:
NB Core Voltage:
CPU VTT Voltage:
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: AUTO
- Enhance Addressing: AUTO
- DIMM 1 CLK fine delay: Current [0]
- DIMM 2 CLK fine delay: Current [5]
- DIMM 3 CLK fine delay: Current [0]
- DIMM 4 CLK fine delay: Current [5]

CAS Latency Time (tCL): 
RAS# to CAS# Delay (tRCD):
RAS# Precharge (tRP):
Precharge Delay (tRAS):
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance Level: AUTO
Read delay phase adjust: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 6
Ranks Read to Read (tRDRD): 6
Ranks Write to Read (tWRRD): 5
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

EDIT:

SetFSB available here thxs to NewBeetle

rlm · 28-08-2007, 06:17 PM

Thanks NCSA

Still battling to get a decent 4-4-4-12 and stable. Spent a few hours or so last night, messing around with settings.

Ran pcmark 05, same spec as the IP35 pro and was about 200 or so behind. Cpu score was better, but memory not so.

Can't get the Geil to run even below spec i.e. 1040mhz 4-4-4-12 and stable. Did manage an 830 mhz 3-3-3-8 though.

Some real vdimm droop by the looks of it. For instance setting vdimm to 2.25-27v in bios with my Gskills. SMG reads 2.22v. When blending this then drops to 2.18v. Could explain in part the stability issues. The gskill is more stable than the Geil though.

Have updated bios now to 823, so will do some more tests later

RLM

rlm · 29-08-2007, 08:06 AM

My superPI 1M Challenge.

I've been messing around with subtimings etc manually in the bios. Haven't touched the phase option yet though.

Does anyone else notice that the scroll bar doesn't go all the way down in the dram settings. What are they hiding?

So far have struggled to get on par with the IP35 pro. I need a lot tighter timings to do that, and obviously stability goes out the window.

Maybe I still need to mess around with some of the non-memset subtimings in bios still. If not I'm convinced they could improve things in a future bios. Would love to see "VDIMM droop control" as well. Maybe wishful thinking.

SuperPi1M ABIT IP35 Pro 415x9 4-4-4-10 2.3v Gskill 6400 GBHZ

SuperPi1M DFI P35-T2R 415x9 4-4-4-10 2.3v Gskill 6400 GBHZ

SuperPi1M DFI P35-T2R 415x9 4-4-4-7 2.3v Gskill 6400 GBHZ

I'll post up my bios settings later, but need to crash out now

RLM

ncsa · 30-08-2007, 03:40 AM

Some interesting notes on the BIOS.. esp on CLK Fine delay ...

Extract from OnePageBook

The best tuning range for finding the best DATA operating phase will be 3 ranks before or after this current value.

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