DFI LP UT X48-T3RS / X48-T2R Bios Templates

05:07 PM

Click on link to show relevant bios screen image. Plain text file version is attached to this post below.

DFI LP UT X48-T3RS 714 Beta Bios
Settings Template

714 beta bios
- Updated the 6/4 beta template with 714 beta template settings but haven't updated screenshots yet as there's more bios updates to come.

PC Health Status
Adjust CPU Temp: Auto

CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
O.C. Fail retry Counter 0
CPU Clock Ratio: 9x
CPU N/2 Ratio: Disabled
Target CPU Clock:
CPU Clock: 333
Boot Up Clock: AUTO
CPU Clock Amplitude: 800mv
CPU Clock0 Skew: 0ps
CPU Clock1 Skew: 0ps
DRAM Speed: 333/1333
- Target DRAM Speed: DDR3-1333
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.10000v
COY VID Special Add Limit: Enabled
CPU VID Special Add: AUT0
DRAM Voltage Control: 1.57v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.430
CPU VTT Voltage: 1.100
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
x MCH RON Offset Value:
x MCH RTT Offset Value:
x MCH Slew Rate Offset Value:
x MCH VREF 1 Value:
x MCH VREF 2 Value:
x MCH VREF 3 Value:

GTL REF Voltage Control: Disable
x CPU GTL 1/2 REF Volt: 113
x CPU GTL 0/3 REF Volt: 100
x North Bridge GTL REF Volt: 100

DRAM Timing
- DRAM CLK Driving Strength: Level 6
- DRAM DATA Driving Strength: Level 8
- Ch1 DLL Default Skew Model: Model 0
- Ch2 DLL Default Skew Model: Model 0
- Enhance Data transmitting: AUTO
- Enhance Addressing: AUTO
- T2 Dispatch: AUTO

Fine Delay Step Degree: 5ps to 80ps

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: AUTO
- DIMM 1 Clock fine delay: Current
- DIMM 2 Clock fine delay: Current
- DIMM 2 Control fine delay: Current
- DIMM 1 Control fine delay: Current
- Ch 1 Command fine delay: Current

Ch2 Clock Crossing Setting: AUTO
- DIMM 3 Clock fine delay: Current
- DIMM 4 Clock fine delay: Current
- DIMM 4 Control fine delay: Current
- DIMM 3 Control fine delay: Current
- Ch 2 Command fine delay: Current

Ch1Ch2 CommonClock Setting: AUTO

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

Common CMD to CS Timing: AUTO/1N/2N (command rate)

CAS Latency Time (tCL): 8
RAS# to CAS# Delay (tRCD): 8
RAS# Precharge (tRP): 8
Precharge Delay (tRAS): 27
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): Auto
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO
- Channel 1 Phase 1 Pull-In: AUTO
- Channel 1 Phase 2 Pull-In: AUTO
- Channel 1 Phase 3 Pull-In: AUTO
- Channel 1 Phase 4 Pull-In: AUTO

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO
XMP Support: Disabled

DFI LP UT X48-T3RS 6/4 Beta Bios
Settings Template

6/4 beta bios

Code:

PC Health Status
Adjust CPU Temp: Auto

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
O.C. Fail retry Counter 0
CPU Clock Ratio: 9x
CPU N/2 Ratio: Disabled
Target CPU Clock:
CPU Clock: 333
Boot Up Clock: AUTO
CPU Clock Amplitude: 800mv
CPU Clock0 Skew: 0ps
CPU Clock1 Skew: 0ps
DRAM Speed: 333/1333
- Target DRAM Speed: DDR3-1333
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.10000v
COY VID Special Add Limit: Enabled
CPU VID Special Add: AUT0
DRAM Voltage Control: 1.57v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.430
CPU VTT Voltage: 1.100
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
x MCH RON Offset Value:
x MCH RTT Offset Value:
x MCH Slew Rate Offset Value:
x MCH VREF 1 Value:
x MCH VREF 2 Value: 
x MCH VREF 3 Value:

GTL REF Voltage Control: Disable
x CPU GTL 1/2 REF Volt: 113
x CPU GTL 0/3 REF Volt: 100
x North Bridge GTL REF Volt: 100

DRAM Timing
- Enhance Data transmitting: Auto
- Enhance Addressing: Auto
- T2 Dispatch: Auto

DRAM Default Skew Model: Model 0 to 3

Fine Delay Step Degree: 5ps to 80ps

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: AUTO
- DIMM 1 Clock fine delay: Current
- DIMM 2 Clock fine delay: Current
- DIMM 2 Control fine delay: Current
- DIMM 1 Control fine delay: Current
- Ch 1 Command fine delay: Current

Ch2 Clock Crossing Setting: AUTO
- DIMM 3 Clock fine delay: Current
- DIMM 4 Clock fine delay: Current
- DIMM 4 Control fine delay: Current
- DIMM 3 Control fine delay: Current
- Ch 2 Command fine delay: Current

Ch1Ch2 CommonClock Setting: AUTO

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

Common CMD to CS Timing: AUTO/1N/2N (command rate)

CAS Latency Time (tCL): 8
RAS# to CAS# Delay (tRCD): 8
RAS# Precharge (tRP): 8
Precharge Delay (tRAS): 27
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): Auto
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO
- Channel 1 Phase 1 Pull-In: AUTO
- Channel 1 Phase 2 Pull-In: AUTO
- Channel 1 Phase 3 Pull-In: AUTO
- Channel 1 Phase 4 Pull-In: AUTO

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

DFI LP UT X48-T3RS 5/21 Official Bios
Settings Template

5/21 official bios

Code:

PC Health Status
Adjust CPU Temp: Auto

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
O.C. Fail retry Counter 0
CPU Clock Ratio: 9x
CPU N/2 Ratio: Disabled
Target CPU Clock:
CPU Clock: 333
Boot Up Clock: AUTO
CPU Clock Amplitude: 800mv
CPU Clock0 Skew: 0ps
CPU Clock1 Skew: 0ps
DRAM Speed: 333/1333
- Target DRAM Speed: DDR3-1333
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.10000v
COY VID Special Add Limit: Enabled
CPU VID Special Add: AUT0
DRAM Voltage Control: 1.57v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.430
CPU VTT Voltage: 1.100
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: Auto
- Enhance Addressing: Auto
- T2 Dispatch: Auto

DLL Mode: Mode 0

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: AUTO
- DIMM 1 Clock fine delay: Current
- DIMM 2 Clock fine delay: Curren
- DIMM 1 Control fine delay: Current
- DIMM 2 Control fine delay: Current
- Ch 1 Command fine delay: Current

Ch2 Clock Crossing Setting: AUTO
- DIMM 3 Clock fine delay: Current
- DIMM 4 Clock fine delay: Current
- DIMM 3 Control fine delay: Current
- DIMM 4 Control fine delay: Current
- Ch 2 Command fine delay: Current

Ch1Ch2 CommonClock Setting: AUTO

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

CAS Latency Time (tCL): 8
RAS# to CAS# Delay (tRCD): 8
RAS# Precharge (tRP): 8
Precharge Delay (tRAS): 27
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): Auto
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO
- Channel 1 Phase 1 Pull-In: AUTO
- Channel 1 Phase 2 Pull-In: AUTO
- Channel 1 Phase 3 Pull-In: AUTO
- Channel 1 Phase 4 Pull-In: AUTO

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO
CMD to CST mode: AUTO/1T/2T

07-06-2008, 06:34 PM #2 (**permalink**)

DFI LP UT X48-T2RS Bios Settings Template

coming soon....