DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly]
This is a discussion on DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] within the DFI Intel Motherboard / CPU forums, part of the Intel motherboards / CPU category; 2x1GB Crucial Ballistix PC2-8500 Tracer @659Mhz 5-5-5-9 at 2.38v Even better, 640mhz 5-5-5-9 at 2.19v, 643mhz 5-5-5-9 at 2.23v and ...
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25-12-2007, 01:09 AM
| #9 (permalink) |
| Administrator | Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] 2x1GB Crucial Ballistix PC2-8500 Tracer @659Mhz 5-5-5-9 at 2.38v Even better, 640mhz 5-5-5-9 at 2.19v, 643mhz 5-5-5-9 at 2.23v and now 659mhz 5-5-5-9 at 2.38v !
DFI LP LT X38-T2R Bios Settings Code: PC Health Status Adjust CPU Temp: +7C CPU Feature - Thermal Management Control: Disabled - PPM(EIST) Mode: Disabled - Limit CPUID MaxVal: Disabled - CIE Function: Disabled - Execute Disable Bit: Disabled - Virtualization Technology: Disabled - Core Multi-Processing: Enabled Exist Setup Shutdown: Mode 2 Shutdown after AC Loss: Disabled CLOCK VC0 divider: AUTO CPU Clock Ratio Unlock: Enabled CPU Clock Ratio: 8x - Target CPU Clock: 3515 CPU Clock: 439 Boot Up Clock: AUTO DRAM Speed: 266/800 - Target DRAM Speed: 1320 PCIE Clock: 100mhz PCIE Slot Config: 1X 1X CPU Spread Spectrum: Disabled PCIE Spread Spectrum: Disabled SATA Spread Spectrum: Disabled Voltage Settings CPU VID Control: 1.2875 CPU VID Special Add: AUTO DRAM Voltage Control: 2.38 SB Core/CPU PLL Voltage: 1.51 NB Core Voltage: 1.604 CPU VTT Voltage: 1.387 Vcore Droop Control: Enabled Clockgen Voltage Control: 3.45v GTL+ Buffers Strength: Strong Host Slew Rate: Weak GTL REF Voltage Control: Disable x CPU GTL1/3 REF Volt: 110 x CPU GTL 0/2 REF Volt: 110 x North Bridge GTL REF Volt: 110 DRAM Timing - Enhance Data transmitting: FAST - Enhance Addressing: FAST - T2 Dispatch: Enabled Clock Setting Fine Delay Ch1 Clock Crossing Setting: More Aggressive - DIMM 1 Clock fine delay: 7 (raised from Current 2) - DIMM 2 Clock fine delay: 7 - Ch 1 Command fine delay: 10 - Ch 1 Control fine delay: 7 Ch2 Clock Crossing Setting: More Aggressive - DIMM 3 Clock fine delay: 7 (raised from Current 2) - DIMM 4 Clock fine delay: 6 - Ch 2 Command fine delay: 10 - Ch 2 Control fine delay: 6 Ch1Ch2 CommonClock Setting: More Aggressive Ch1 RDCAS GNT-Chip Delay: Auto Ch1 WRCAS GNT-Chip Delay: Auto Ch1 Command to CS Delay: Auto Ch2 RDCAS GNT-Chip Delay: Auto Ch2 WRCAS GNT-Chip Delay: Auto Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING) CAS Latency Time (tCL): 5 RAS# to CAS# Delay (tRCD): 5 RAS# Precharge (tRP): 5 Precharge Delay (tRAS): 9 All Precharge to Act: 4 REF to ACT Delay (tRFC): 30 Performance LVL (Read Delay) (tRD): 6 Read delay phase adjust: Enter Ch1 Read delay phase (4~0) - Channel 1 Phase 0 Pull-In: Auto - Channel 1 Phase 1 Pull-In: Auto - Channel 1 Phase 2 Pull-In: Auto - Channel 1 Phase 3 Pull-In: Auto - Channel 1 Phase 4 Pull-In: Auto Ch2 Read delay phase (4~0) - Channel 2 Phase 0 Pull-In: Auto - Channel 2 Phase 1 Pull-In: Auto - Channel 2 Phase 2 Pull-In: Auto - Channel 2 Phase 3 Pull-In: Auto - Channel 2 Phase 4 Pull-In: Auto MCH ODT Latency: AUTO Write to PRE Delay (tWR): 14 Rank Write to Read (tWTR): 11 ACT to ACT Delay (tRRD): 3 Read to Write Delay (tRDWR): 8 Ranks Write to Write (tWRWR): 4 Ranks Read to Read (tRDRD): 5 Ranks Write to Read (tWRRD): 4 Read CAS# Precharge (tRTP): 3 ALL PRE to Refresh: 4 |
| Last edited by eva2000; 20-05-2008 at 06:44 AM. | |
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25-12-2007, 01:09 AM
| #10 (permalink) |
| Administrator | Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] 2x1GB Crucial Ballistix PC2-8500 Tracer @601Mhz 4-4-4-9 at 2.55v DFI LP LT X38-T2R is the first motherboard ever for me to allow me to pass Super Pi 32M at 600mhz 4-4-4-x settings below <2.60v memory voltage. After fine tuning clock and command fine delay I managed to pull off 32M @601.9Mhz 4-4-4-9 at 2.55v straight boot from bios. Then using Memset tightened tRFC and tRAS and tWR to 25, 8 and 11 (bios or 10 memset) respectively and still pass a Super Pi 32M run. Unfortunately, it seems the Super Pi 32M time on DFI LP LT X38-T2R even at 9x401FSB 601.9Mhz 4-4-4-9 was around 2-4 seconds slower than on DFI LP UT P35-T2R @9x400FSB 600Mhz 5-4-4-5 at basically same timings/subtimings and bios tweaks. @601.9Mhz 4-4-4-9 at 2.55v Tightened subtimings in Memset (same windows session) It seems to come down to bandwidth and latency differences between DFI LP LT X38-T2R vs LP UT P35-T2R. X38-T2R P35-T2R Yes, tRFC and tWR is a bit tighter at 24 and 10 instead of 30 and 14 but that didn't make up for super pi or everest bandwidth differences much. DFI LP LT X38-T2R Bios Settings Code: PC Health Status Adjust CPU Temp: +7C CPU Feature - Thermal Management Control: Disabled - PPM(EIST) Mode: Disabled - Limit CPUID MaxVal: Disabled - CIE Function: Disabled - Execute Disable Bit: Disabled - Virtualization Technology: Disabled - Core Multi-Processing: Enabled Exist Setup Shutdown: Mode 2 Shutdown after AC Loss: Disabled CLOCK VC0 divider: AUTO CPU Clock Ratio Unlock: Enabled CPU Clock Ratio: 9x - Target CPU Clock: 3618 CPU Clock: 402 Boot Up Clock: AUTO DRAM Speed: 266/800 - Target DRAM Speed: 1206 PCIE Clock: 100mhz PCIE Slot Config: 1X 1X CPU Spread Spectrum: Disabled PCIE Spread Spectrum: Disabled SATA Spread Spectrum: Disabled Voltage Settings CPU VID Control: 1.2875 CPU VID Special Add: AUTO DRAM Voltage Control: 2.55 SB Core/CPU PLL Voltage: 1.51 NB Core Voltage: 1.617 CPU VTT Voltage: 1.393 Vcore Droop Control: Enabled Clockgen Voltage Control: 3.45v GTL+ Buffers Strength: Strong Host Slew Rate: Weak GTL REF Voltage Control: Disable x CPU GTL1/3 REF Volt: 110 x CPU GTL 0/2 REF Volt: 110 x North Bridge GTL REF Volt: 110 DRAM Timing - Enhance Data transmitting: FAST - Enhance Addressing: FAST - T2 Dispatch: Enabled Clock Setting Fine Delay Ch1 Clock Crossing Setting: More Aggressive - DIMM 1 Clock fine delay: 6 - DIMM 2 Clock fine delay: 5 - Ch 1 Command fine delay: 9 - Ch 1 Control fine delay: 5 Ch2 Clock Crossing Setting: More Aggressive - DIMM 3 Clock fine delay: 6 - DIMM 4 Clock fine delay: 4 - Ch 2 Command fine delay: 9 - Ch 2 Control fine delay: 4 Ch1Ch2 CommonClock Setting: More Aggressive Ch1 RDCAS GNT-Chip Delay: Auto Ch1 WRCAS GNT-Chip Delay: Auto Ch1 Command to CS Delay: Auto Ch2 RDCAS GNT-Chip Delay: Auto Ch2 WRCAS GNT-Chip Delay: Auto Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING) CAS Latency Time (tCL): 4 RAS# to CAS# Delay (tRCD): 4 RAS# Precharge (tRP): 4 Precharge Delay (tRAS): 9 All Precharge to Act: 4 REF to ACT Delay (tRFC): 30 Performance LVL (Read Delay) (tRD): 5 Read delay phase adjust: Enter Ch1 Read delay phase (4~0) - Channel 1 Phase 0 Pull-In: Auto - Channel 1 Phase 1 Pull-In: Auto - Channel 1 Phase 2 Pull-In: Auto - Channel 1 Phase 3 Pull-In: Auto - Channel 1 Phase 4 Pull-In: Auto Ch2 Read delay phase (4~0) - Channel 2 Phase 0 Pull-In: Auto - Channel 2 Phase 1 Pull-In: Auto - Channel 2 Phase 2 Pull-In: Auto - Channel 2 Phase 3 Pull-In: Auto - Channel 2 Phase 4 Pull-In: Auto MCH ODT Latency: AUTO Write to PRE Delay (tWR): 14 Rank Write to Read (tWTR): 11 ACT to ACT Delay (tRRD): 3 Read to Write Delay (tRDWR): 8 Ranks Write to Write (tWRWR): 4 Ranks Read to Read (tRDRD): 5 Ranks Write to Read (tWRRD): 4 Read CAS# Precharge (tRTP): 3 ALL PRE to Refresh: 4 |
| Last edited by eva2000; 20-05-2008 at 06:46 AM. | |
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25-12-2007, 01:09 AM
| #11 (permalink) |
| Administrator | Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] 2x1GB Crucial Ballistix PC2-8500 Tracer @675Mhz 5-5-5-9 at 2.55v Swapped the dimm slots for this pair of Crucial Ballistix PC2-8500 Tracers from dimm slot 2+4 (yellow slots) to 1+3 (green slots) and seems can overclock a bit better. I can now hit 675Mhz 5-5-5-9 at 2.55v - highest ever CAS5 memory clock for this pair of Crucial Ballistix PC2-8500 Tracers at Super Pi 32M passable speeds! Still 32M time seems around 4-10 seconds slower at 3600Mhz mark than 965P/P35 chipset. I guess the loosened internal latencies on X38 allow memory to clock higher but at a cost of clock for clock performance ? Still I am looking forward to 3dmark benchmarks with X38 x16+x16 PCI-E slots  Managed to shave 4 seconds off 32M time and drop memory latency a tad DFI LP LT X38-T2R Bios Settings Code: PC Health Status Adjust CPU Temp: +7C CPU Feature - Thermal Management Control: Disabled - PPM(EIST) Mode: Disabled - Limit CPUID MaxVal: Disabled - CIE Function: Disabled - Execute Disable Bit: Disabled - Virtualization Technology: Disabled - Core Multi-Processing: Enabled Exist Setup Shutdown: Mode 2 Shutdown after AC Loss: Disabled CLOCK VC0 divider: AUTO CPU Clock Ratio Unlock: Enabled CPU Clock Ratio: 8x - Target CPU Clock: 3601 CPU Clock: 450 Boot Up Clock: AUTO DRAM Speed: 266/800 - Target DRAM Speed: 1353 PCIE Clock: 100mhz PCIE Slot Config: 1X 1X CPU Spread Spectrum: Disabled PCIE Spread Spectrum: Disabled SATA Spread Spectrum: Disabled Voltage Settings CPU VID Control: 1.2875 CPU VID Special Add: AUTO DRAM Voltage Control: 2.55 SB Core/CPU PLL Voltage: 1.51 NB Core Voltage: 1.643 CPU VTT Voltage: 1.393 Vcore Droop Control: Enabled Clockgen Voltage Control: 3.45v GTL+ Buffers Strength: Strong Host Slew Rate: Weak GTL REF Voltage Control: Disable x CPU GTL1/3 REF Volt: 110 x CPU GTL 0/2 REF Volt: 110 x North Bridge GTL REF Volt: 110 DRAM Timing - Enhance Data transmitting: FAST - Enhance Addressing: FAST - T2 Dispatch: Enabled Clock Setting Fine Delay Ch1 Clock Crossing Setting: More Aggressive - DIMM 1 Clock fine delay: 6 - DIMM 2 Clock fine delay: 7 - Ch 1 Command fine delay: 11 - Ch 1 Control fine delay: 8 Ch2 Clock Crossing Setting: More Aggressive - DIMM 3 Clock fine delay: 6 - DIMM 4 Clock fine delay: 7 - Ch 2 Command fine delay: 11 - Ch 2 Control fine delay: 6 Ch1Ch2 CommonClock Setting: More Aggressive Ch1 RDCAS GNT-Chip Delay: Auto Ch1 WRCAS GNT-Chip Delay: Auto Ch1 Command to CS Delay: Auto Ch2 RDCAS GNT-Chip Delay: Auto Ch2 WRCAS GNT-Chip Delay: Auto Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING) CAS Latency Time (tCL): 4 RAS# to CAS# Delay (tRCD): 4 RAS# Precharge (tRP): 4 Precharge Delay (tRAS): 5 All Precharge to Act: 4 REF to ACT Delay (tRFC): 30 Performance LVL (Read Delay) (tRD): 5 Read delay phase adjust: Enter Ch1 Read delay phase (4~0) - Channel 1 Phase 0 Pull-In: Auto - Channel 1 Phase 1 Pull-In: Auto - Channel 1 Phase 2 Pull-In: Auto - Channel 1 Phase 3 Pull-In: Auto - Channel 1 Phase 4 Pull-In: Auto Ch2 Read delay phase (4~0) - Channel 2 Phase 0 Pull-In: Auto - Channel 2 Phase 1 Pull-In: Auto - Channel 2 Phase 2 Pull-In: Auto - Channel 2 Phase 3 Pull-In: Auto - Channel 2 Phase 4 Pull-In: Auto MCH ODT Latency: AUTO Write to PRE Delay (tWR): 14 Rank Write to Read (tWTR): 11 ACT to ACT Delay (tRRD): 3 Read to Write Delay (tRDWR): 8 Ranks Write to Write (tWRWR): 4 Ranks Read to Read (tRDRD): 5 Ranks Write to Read (tWRRD): 4 Read CAS# Precharge (tRTP): 3 ALL PRE to Refresh: 4 |
| Last edited by eva2000; 20-05-2008 at 06:46 AM. | |
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25-12-2007, 01:09 AM
| #12 (permalink) |
| Administrator | Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] 2x1GB Crucial Ballistix PC2-8500 Tracer @681.5Mhz 5-5-5-9 at 2.60v Bumped up vdimm and 32M @681.5Mhz 5-5-5-9 at 2.60v ! DFI LP LT X38-T2R Bios Settings Code: PC Health Status Adjust CPU Temp: +7C CPU Feature - Thermal Management Control: Disabled - PPM(EIST) Mode: Disabled - Limit CPUID MaxVal: Disabled - CIE Function: Disabled - Execute Disable Bit: Disabled - Virtualization Technology: Disabled - Core Multi-Processing: Enabled Exist Setup Shutdown: Mode 2 Shutdown after AC Loss: Disabled CLOCK VC0 divider: AUTO CPU Clock Ratio Unlock: Enabled CPU Clock Ratio: 8x - Target CPU Clock: 3634 CPU Clock: 454 Boot Up Clock: AUTO DRAM Speed: 266/800 - Target DRAM Speed: 1364 PCIE Clock: 100mhz PCIE Slot Config: 1X 1X CPU Spread Spectrum: Disabled PCIE Spread Spectrum: Disabled SATA Spread Spectrum: Disabled Voltage Settings CPU VID Control: 1.325 CPU VID Special Add: AUTO DRAM Voltage Control: 2.60 SB Core/CPU PLL Voltage: 1.51 NB Core Voltage: 1.665 CPU VTT Voltage: 1.409 Vcore Droop Control: Enabled Clockgen Voltage Control: 3.45v GTL+ Buffers Strength: Strong Host Slew Rate: Weak GTL REF Voltage Control: Disable x CPU GTL1/3 REF Volt: 110 x CPU GTL 0/2 REF Volt: 110 x North Bridge GTL REF Volt: 110 DRAM Timing - Enhance Data transmitting: FAST - Enhance Addressing: FAST - T2 Dispatch: Enabled Clock Setting Fine Delay Ch1 Clock Crossing Setting: More Aggressive - DIMM 1 Clock fine delay: 6 - DIMM 2 Clock fine delay: 7 - Ch 1 Command fine delay: 11 - Ch 1 Control fine delay: 8 Ch2 Clock Crossing Setting: More Aggressive - DIMM 3 Clock fine delay: 6 - DIMM 4 Clock fine delay: 7 - Ch 2 Command fine delay: 11 - Ch 2 Control fine delay: 6 Ch1Ch2 CommonClock Setting: More Aggressive Ch1 RDCAS GNT-Chip Delay: Auto Ch1 WRCAS GNT-Chip Delay: Auto Ch1 Command to CS Delay: Auto Ch2 RDCAS GNT-Chip Delay: Auto Ch2 WRCAS GNT-Chip Delay: Auto Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING) CAS Latency Time (tCL): 4 RAS# to CAS# Delay (tRCD): 4 RAS# Precharge (tRP): 4 Precharge Delay (tRAS): 5 All Precharge to Act: 4 REF to ACT Delay (tRFC): 30 Performance LVL (Read Delay) (tRD): 5 Read delay phase adjust: Enter Ch1 Read delay phase (4~0) - Channel 1 Phase 0 Pull-In: Enabled - Channel 1 Phase 1 Pull-In: Enabled - Channel 1 Phase 2 Pull-In: Enabled - Channel 1 Phase 3 Pull-In: Enabled - Channel 1 Phase 4 Pull-In: Enabled Ch2 Read delay phase (4~0) - Channel 2 Phase 0 Pull-In: Auto - Channel 2 Phase 1 Pull-In: Auto - Channel 2 Phase 2 Pull-In: Enabled - Channel 2 Phase 3 Pull-In: Enabled - Channel 2 Phase 4 Pull-In: Enabled MCH ODT Latency: AUTO Write to PRE Delay (tWR): 14 Rank Write to Read (tWTR): 11 ACT to ACT Delay (tRRD): 3 Read to Write Delay (tRDWR): 8 Ranks Write to Write (tWRWR): 4 Ranks Read to Read (tRDRD): 5 Ranks Write to Read (tWRRD): 4 Read CAS# Precharge (tRTP): 3 ALL PRE to Refresh: 4 |
| Last edited by eva2000; 20-05-2008 at 06:47 AM. | |
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25-12-2007, 01:10 AM
| #13 (permalink) |
| Administrator | Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] E6850 L720A489 @4005Mhz at 1.472v @4107Mhz at 1.584v Some quick 1hr Prime95 stability sessions just to find out how my E6850 L720A489 does on DFI LP LT X38-T2R.
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| Last edited by eva2000; 20-05-2008 at 06:47 AM. | |
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25-12-2007, 01:10 AM
| #14 (permalink) |
| Administrator | Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] 12/28 Beta Bios - 5:8 divider tests Previously on 11/28 bios, certain memory dividers had stability issues. 4:5 divider couldn't do more than 440FSB, 3:5 divider had issues of stability even at 333FSB due to tight performance level of 4 and 5:8 divider wouldn't even allow system to boot regardless of cpu FSB set. Now 12/28 beta bios http://www.dfi.com.tw/Support/Downlo...FLAG=B&SITE=US has at least moved one step closer, with fixing the 5:8 divider. From 11/28 bios 5:8 no system boot, to 12/28 beta bios doing 400FSB 5:8 640Mhz 5-5-5-15 on memory! Having some difficulties tuning clock fine delay for above 400FSB on 5:8 so far since using 2x1GB Crucial Ballistix PC2-8500 Tracers on 2:3 divider manages upto 681mhz 5-5-5-x more easily! 5:8 divider needs slightly more vdimm than 2:3 divider but still pretty good for 640mhz 5-5-5-15 at 2.35v bios set. Results 12/28 Beta Bios settings Code: PC Health Status Adjust CPU Temp: +7 CPU Feature - Thermal Management Control: Disabled - PPM(EIST) Mode: Disabled - Limit CPUID MaxVal: Disabled - CIE Function: Disabled - Execute Disable Bit: Disabled - Virtualization Technology: Disabled - Core Multi-Processing: Enabled Exist Setup Shutdown: Mode 2 Shutdown after AC Loss: Disabled CLOCK VC0 divider: AUTO CPU Clock Ratio Unlock: Enabled CPU Clock Ratio: 9x - Target CPU Clock: 3600 CPU Clock: 400 Boot Up Clock: AUTO DRAM Speed: 333/1066 - Target DRAM Speed: 1280 PCIE Clock: 100mhz PCIE Slot Config: 1X 1X CPU Spread Spectrum: Disabled PCIE Spread Spectrum: Disabled SATA Spread Spectrum: Disabled Voltage Settings CPU VID Control: 1.2875v CPU VID Special Add: AUTO DRAM Voltage Control: 2.35v SB Core/CPU PLL Voltage: 1.51 NB Core Voltage: 1.566 CPU VTT Voltage: 1.393 Vcore Droop Control: Enabled Clockgen Voltage Control: 3.45v GTL+ Buffers Strength: Strong Host Slew Rate: Weak GTL REF Voltage Control: Disable x CPU GTL1/3 REF Volt: 110 x CPU GTL 0/2 REF Volt: 110 x North Bridge GTL REF Volt: 110 DRAM Timing - Enhance Data transmitting: FAST - Enhance Addressing: FAST - T2 Dispatch: Enabled Clock Setting Fine Delay Ch1 Clock Crossing Setting: More Aggressive - DIMM 1 Clock fine delay: 1680 - DIMM 2 Clock fine delay: 490 - DIMM 1 Control fine delay: 560 - DIMM 2 Control fine delay: 350 - Ch 1 Command fine delay: 350 Ch2 Clock Crossing Setting: More Aggressive - DIMM 3 Clock fine delay: 1610 - DIMM 4 Clock fine delay: 490 - DIMM 3 Control fine delay: 560 - DIMM 4 Control fine delay: 350 - Ch 2 Command fine delay: 280 Ch1Ch2 CommonClock Setting: More Aggressive Ch1 RDCAS GNT-Chip Delay: Auto Ch1 WRCAS GNT-Chip Delay: Auto Ch1 Command to CS Delay: Auto Ch2 RDCAS GNT-Chip Delay: Auto Ch2 WRCAS GNT-Chip Delay: Auto Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING) CAS Latency Time (tCL): 5 RAS# to CAS# Delay (tRCD): 5 RAS# Precharge (tRP): 5 Precharge Delay (tRAS): 15 All Precharge to Act: 4 REF to ACT Delay (tRFC): 35 Performance LVL (Read Delay) (tRD): 7 Read delay phase adjust: Enter Ch1 Read delay phase (4~0) - Channel 1 Phase 0 Pull-In: Auto - Channel 1 Phase 1 Pull-In: Auto - Channel 1 Phase 2 Pull-In: Auto - Channel 1 Phase 3 Pull-In: Auto - Channel 1 Phase 4 Pull-In: Auto Ch2 Read delay phase (4~0) - Channel 2 Phase 0 Pull-In: Auto - Channel 2 Phase 1 Pull-In: Auto - Channel 2 Phase 2 Pull-In: Auto - Channel 2 Phase 3 Pull-In: Auto - Channel 2 Phase 4 Pull-In: Auto MCH ODT Latency: AUTO Write to PRE Delay (tWR): 11 Rank Write to Read (tWTR): 11 ACT to ACT Delay (tRRD): 3 Read to Write Delay (tRDWR): AUTO Ranks Write to Write (tWRWR): AUTO Ranks Read to Read (tRDRD): AUTO Ranks Write to Read (tWRRD): AUTO Read CAS# Precharge (tRTP): 3 ALL PRE to Refresh: 4 |
| Last edited by eva2000; 20-05-2008 at 06:48 AM. | |
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25-12-2007, 01:10 AM
| #15 (permalink) |
| Administrator | Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] DFI LT X38-T2R Other Tests Spent a bit more time with DFI LT X38-T2R since last with other specific tests. Thought I'd link to these tests here as well.
DFI LT X38-T2R R.A03 GTL Ref voltage measurements Decided to get off my butt and do some multimeter measurements for GTL Ref CPU & NB voltages as well for my DFI LT X38-T2R as it's pretty tricky with QX9650 quad core cpus and trying to break 450FSB without tweaking GTL Ref CPU & NB voltages. Measurements read from Clunks' photos read points from DFI provided info. So far these are the measurements I've done for my DFI LT X38-T2R R.A03 revision board with 3/14 official bios and Made in Taiwan PCB. Of interest is seeing what the default GTL Ref volts are when the GTL Ref options are disabled - they default to approximately, 63%, 63% and 67% respectively.  |
| Last edited by eva2000; 08-05-2008 at 01:57 PM. | |
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