|
Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly]
|
25-12-2007, 02:08 AM
#6 (permalink)
|
Update: From 12/28 bios onwards, the Clock fine delay values changed from numeric values 1-14 IIRC, to xxxPS values. Nothing has changed in the
process of finding the optimal Clock fine delay values as outlined at
DFI LP UT P35-T2R / DFI LP LT X38-T2R - working with 'CLK Fine Delay' just the values you select has changed.
Another memory related option in DFI LP LT X38-T2R bios, is Clock Fine Delay - tuning this can have a dramatic effect on boosting your memory overclocking headroom as well as reducing memory voltage needed. A sticky thread can be found
here for some tips on finding optimal clock fine delay values.
You will see some examples below of this
Clock Fine Delay At Work
Still very early into my testing of how memory behave on DFI LP LT X38-T2R with 11/28 bios. It basically seems like a more matured version of what is implemented on DFI LP UT P35-T2R
Playing with 2:3 divider (266/800) and 2x 1GB Crucial Ballistix PC2-8500, I found myself hitting memory clock wall at several points while doing my routine Memtest86+ v1.70 testing.
Only salvation to break through that memory clock wall was fine tuning Clock Fine Delay values for DIMM 1 & 3. To my surprise I broke through that 651Mhz wall and ended up at 666Mhz 5-5-5-9 at 2.49v being single Super Pi 32M stable!
- 633mhz 5-5-5-9 at 2.27v was okay
- 640mhz 5-5-5-9 at 2.31v was okay
- 651mhz 5-5-5-9 regardless of vdimm used kept freezing in test #5 loop testing - clock fine delay was all set to Current.
- 651mhz 5-5-5-9 at 2.38v errored out in memtest, but elimated freezing by increasing dimm 1 + 3 clock fine delay values from Current (2) to manually set 3.
- 660mhz 5-5-5-9 at 2.45v was okay in memtest now by further increasing dimm 1 + 3 clock fine delay values from manually set 3 to 5.
- 666mhz 5-5-5-9 at 2.49v would error out in test #5 loop on 2nd pass with a few errors everytime, no voltage adjustments helped.
- 666mhz 5-5-5-9 at 2.49v was okay when i further increased dimm 1 + 3 clock fine delay values from manually set 5 to 6 or 7.
- 670mhz 5-5-5-9 at 2.49v would error out in test #5 loop on 2nd pass with a few errors everytime, voltage adjustments didn't help much to stablise it. Dimm 1 + 3 clock fine delay values manually set at 7 helped reduce it to a few errors in memtest86+ v1.70 test #5 loop.
So here's where I end up at so far 666Mhz 5-5-5-9 at 2.49v! Pretty awesome for initially having hit a brick wall at 651Mhz 5-5-5-9!
DFI LP LT X38-T2R Bios Settings
Code:
PC Health Status
Adjust CPU Temp: +7C
CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled
Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 8x
- Target CPU Clock: 3552
CPU Clock: 444
Boot Up Clock: AUTO
DRAM Speed: 266/800
- Target DRAM Speed: 1335
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled
Voltage Settings
CPU VID Control: 1.2875
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.49
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.643
CPU VTT Voltage: 1.377
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110
DRAM Timing
- Enhance Data transmitting: FAST
- Enhance Addressing: FAST
- T2 Dispatch: Enabled
Clock Setting Fine Delay
Ch1 Clock Crossing Setting: More Aggressive
- DIMM 1 Clock fine delay: 7 (manually increased from 2 allowed me to pass 651Mhz mem clock wall in memtest86+ v1.70)
- DIMM 2 Clock fine delay: Current 7
- Ch 1 Command fine delay: Current 11
- Ch 1 Control fine delay: Current 8
Ch2 Clock Crossing Setting: More Aggressive
- DIMM 3 Clock fine delay: 7 (manually increased from 2 allowed me to pass 651Mhz mem clock wall in memtest86+ v1.70)
- DIMM 4 Clock fine delay: Current 6
- Ch 2 Command fine delay: Current 11
- Ch 2 Control fine delay: Current 6
Ch1Ch2 CommonClock Setting: More Aggressive
Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto
Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)
CAS Latency Time (tCL): 5
RAS# to CAS# Delay (tRCD): 5
RAS# Precharge (tRP): 5
Precharge Delay (tRAS): 9
All Precharge to Act: 4
REF to ACT Delay (tRFC): 30
Performance LVL (Read Delay) (tRD): 6
Read delay phase adjust: Enter
Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: Auto
- Channel 1 Phase 1 Pull-In: Auto
- Channel 1 Phase 2 Pull-In: Auto
- Channel 1 Phase 3 Pull-In: Auto
- Channel 1 Phase 4 Pull-In: Auto
Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): 14
Rank Write to Read (tWTR): 11
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 4
Ranks Read to Read (tRDRD): 5
Ranks Write to Read (tWRRD): 4
Read CAS# Precharge (tRTP): 3
ALL PRE to Refresh: 4
Again clock fine delay and controller fine delay tweaking allowed me to stabilize my 2x 1GB Crucial Ballistix PC2-8500 @585Mhz 4-4-4-5 PL 5 at 2.51v.
- 540mhz 4-4-4-5 at 2.23v = okay
- 550mhz 4-4-4-5 at 2.31v = okay
- 565mhz 4-4-4-5 at 2.38v = okay
- 575mhz 4-4-4-5 at 2.45v = okay
- 580mhz 4-4-4-5 at 2.47v = okay
- 585mhz 4-4-4-5 at 2.49v = 4 errors in 1st pass of test #5 memtest86+ v1.70 loop
- 585mhz 4-4-4-5 at 2.51v = okay (manually set clock fine delay from current 3 to 4 and control fine delay for DIMM 1 + 3 changed from current 10 to manually set 11)
DFI LP LT X38-T2R Bios Settings
Code:
PC Health Status
Adjust CPU Temp: +7C
CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled
Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 9x
- Target CPU Clock: 3552
CPU Clock: 390
Boot Up Clock: AUTO
DRAM Speed: 266/800
- Target DRAM Speed: 1172
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled
Voltage Settings
CPU VID Control: 1.2875
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.51
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.555
CPU VTT Voltage: 1.377
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110
DRAM Timing
- Enhance Data transmitting: FAST
- Enhance Addressing: FAST
- T2 Dispatch: Enabled
Clock Setting Fine Delay
Ch1 Clock Crossing Setting: More Aggressive
- DIMM 1 Clock fine delay: 4 (manually increased from 3)
- DIMM 2 Clock fine delay: 6 (manually set from current 6)
- Ch 1 Command fine delay: 11 (manually increased from current 10)
- Ch 1 Control fine delay: 7 (manually set from current 7)
Ch2 Clock Crossing Setting: More Aggressive
- DIMM 3 Clock fine delay: 4 (manually increased from 3)
- DIMM 4 Clock fine delay: 6 (manually set from current 6)
- Ch 2 Command fine delay: 11 (manually increased from current 10)
- Ch 2 Control fine delay: 5 (manually set from current 5)
Ch1Ch2 CommonClock Setting: More Aggressive
Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto
Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)
CAS Latency Time (tCL): 4
RAS# to CAS# Delay (tRCD): 4
RAS# Precharge (tRP): 4
Precharge Delay (tRAS): 5
All Precharge to Act: 4
REF to ACT Delay (tRFC): 30
Performance LVL (Read Delay) (tRD): 5
Read delay phase adjust: Enter
Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: Auto
- Channel 1 Phase 1 Pull-In: Auto
- Channel 1 Phase 2 Pull-In: Auto
- Channel 1 Phase 3 Pull-In: Auto
- Channel 1 Phase 4 Pull-In: Auto
Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): 14
Rank Write to Read (tWTR): 11
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 4
Ranks Read to Read (tRDRD): 5
Ranks Write to Read (tWRRD): 4
Read CAS# Precharge (tRTP): 3
ALL PRE to Refresh: 4
DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly]
