DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly]
This is a discussion on DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] within the DFI Intel Motherboard / CPU forums, part of the Intel motherboards / CPU category; DFI Lanparty LT X38-T2R Info, overclocking tips & photos [56k user friendly] Short url: http://i4memory.com/dfix38/ Christmas post this is - ...
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25-12-2007, 01:06 AM
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| Administrator |  DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] DFI Lanparty LT X38-T2R Info, overclocking tips & photos [56k user friendly] Short url: http://i4memory.com/dfix38/ Christmas post this is - thought I'd share something special with you folks this time round. I've decided to compile this thread differently from my previous motherboard threads, in that I will try to make it as 56k user friendly as possible - pretty hard for me as you know, I love my screenshots  Thanks to DFI Taiwan, I've been playing with this DFI Lanparty LT X38-T2R for the past 11 days. Still using the initial out of the box bios release which is 11/28 bios. [Click thumbnail for larger version, use keyboard arrow keys to cycle through images]             View more images here. Used Artic Cooling MX-2 thermal paste on northbridge and replaced SB and PWM heatsinks' thermal paste with MX-2 as well. Installing WinXP Pro SP2 right now  Downloads:
Latest Official bios:
Latest beta bios:
Some folks asked why cpu heatsink can't be oriented the other way with fan exhausting from back of case. Best I can do to explain, is take a photo of HR-05 side on with stock DFI X38 heatsink to compare. As far as I can tell the stock DFI LT X38 NB heatsink's wider base is what blocks the Thermalright Ultra 120 Extreme's heatpipes from being oriented the way where fan exhausts air out of case. (click thumbnail for larger version)   Not 100% sure but hope that helps some folks. |
| Last edited by eva2000; 23-01-2009 at 01:20 PM. | |
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25-12-2007, 01:07 AM
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| Administrator | Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] Bios Screenshots Will upload later DFI LP LT X38-T2R Bios Settings Template
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25-12-2007, 01:07 AM
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| Administrator | Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] Info, tips and issues:
System specs
Vcore seems to overvolt - but i have loadline calibration enabled. So will see how it does disabled. Vcore = 1.3125v bios set = 1.344v With Samsung 750GB 32MB HD753LJ SATA disk on DFI LP LT X38-T2R as OS drive. Installed multi-boot windows on several partitions. This is what HDTACH and HDTune looked like on OS drive Not bad I must say for a populated drive |
| Last edited by eva2000; 20-05-2008 at 06:40 AM. | |
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25-12-2007, 01:07 AM
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| Administrator | Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] E6850 @3600Mhz at 1.312v E6850 on the DFI LT X38-T2R with Thermalright Ultra 120 Extreme + 120x38mm Panaflo 103cfm fan positioned the way pictured below  Bios set vcore = 1.2875v Room temp = 25.3C to 28.8C |
| Last edited by eva2000; 20-05-2008 at 06:40 AM. | |
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25-12-2007, 01:07 AM
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| Administrator | Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly]
DFI LP LT X38-T2R has an awesome memory related bios option to adjust read delay phases - basically away of tweaking tRD / performance levels between the set tRD / performance level and the level below it. This can squeeze out a bit more performance in your memory and may help high FSB/memory clocking situations as well. Read delay phase adjusts - all AUTO Update: Seems the best way to tweak this is to work with enabling read delay phase adjustments only on Channel 1, leaving Channel 2's read delay phase adjustments on AUTO. I found the last 3 Phase pull-in settings on each channel don't do much at all for memory performance or latencies when enabled. Only the first 2 phase pull-ins can alter performance. Maybe because my subtimings are already tight ?? Read delay phases - last 3 Phase pull-in settings enabled - 1st and 2nd Phase pull-in settings AUTO |
| Last edited by eva2000; 20-05-2008 at 06:41 AM. | |
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25-12-2007, 01:08 AM
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| Administrator | Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] Update: From 12/28 bios onwards, the Clock fine delay values changed from numeric values 1-14 IIRC, to xxxPS values. Nothing has changed in the process of finding the optimal Clock fine delay values as outlined at DFI LP UT P35-T2R / DFI LP LT X38-T2R - working with 'CLK Fine Delay' just the values you select has changed. Another memory related option in DFI LP LT X38-T2R bios, is Clock Fine Delay - tuning this can have a dramatic effect on boosting your memory overclocking headroom as well as reducing memory voltage needed. A sticky thread can be found here for some tips on finding optimal clock fine delay values. You will see some examples below of this Clock Fine Delay At Work Still very early into my testing of how memory behave on DFI LP LT X38-T2R with 11/28 bios. It basically seems like a more matured version of what is implemented on DFI LP UT P35-T2R Playing with 2:3 divider (266/800) and 2x 1GB Crucial Ballistix PC2-8500, I found myself hitting memory clock wall at several points while doing my routine Memtest86+ v1.70 testing. Only salvation to break through that memory clock wall was fine tuning Clock Fine Delay values for DIMM 1 & 3. To my surprise I broke through that 651Mhz wall and ended up at 666Mhz 5-5-5-9 at 2.49v being single Super Pi 32M stable!
So here's where I end up at so far 666Mhz 5-5-5-9 at 2.49v! Pretty awesome for initially having hit a brick wall at 651Mhz 5-5-5-9! DFI LP LT X38-T2R Bios Settings Code: PC Health Status Adjust CPU Temp: +7C CPU Feature - Thermal Management Control: Disabled - PPM(EIST) Mode: Disabled - Limit CPUID MaxVal: Disabled - CIE Function: Disabled - Execute Disable Bit: Disabled - Virtualization Technology: Disabled - Core Multi-Processing: Enabled Exist Setup Shutdown: Mode 2 Shutdown after AC Loss: Disabled CLOCK VC0 divider: AUTO CPU Clock Ratio Unlock: Enabled CPU Clock Ratio: 8x - Target CPU Clock: 3552 CPU Clock: 444 Boot Up Clock: AUTO DRAM Speed: 266/800 - Target DRAM Speed: 1335 PCIE Clock: 100mhz PCIE Slot Config: 1X 1X CPU Spread Spectrum: Disabled PCIE Spread Spectrum: Disabled SATA Spread Spectrum: Disabled Voltage Settings CPU VID Control: 1.2875 CPU VID Special Add: AUTO DRAM Voltage Control: 2.49 SB Core/CPU PLL Voltage: 1.51 NB Core Voltage: 1.643 CPU VTT Voltage: 1.377 Vcore Droop Control: Enabled Clockgen Voltage Control: 3.45v GTL+ Buffers Strength: Strong Host Slew Rate: Weak GTL REF Voltage Control: Disable x CPU GTL1/3 REF Volt: 110 x CPU GTL 0/2 REF Volt: 110 x North Bridge GTL REF Volt: 110 DRAM Timing - Enhance Data transmitting: FAST - Enhance Addressing: FAST - T2 Dispatch: Enabled Clock Setting Fine Delay Ch1 Clock Crossing Setting: More Aggressive - DIMM 1 Clock fine delay: 7 (manually increased from 2 allowed me to pass 651Mhz mem clock wall in memtest86+ v1.70) - DIMM 2 Clock fine delay: Current 7 - Ch 1 Command fine delay: Current 11 - Ch 1 Control fine delay: Current 8 Ch2 Clock Crossing Setting: More Aggressive - DIMM 3 Clock fine delay: 7 (manually increased from 2 allowed me to pass 651Mhz mem clock wall in memtest86+ v1.70) - DIMM 4 Clock fine delay: Current 6 - Ch 2 Command fine delay: Current 11 - Ch 2 Control fine delay: Current 6 Ch1Ch2 CommonClock Setting: More Aggressive Ch1 RDCAS GNT-Chip Delay: Auto Ch1 WRCAS GNT-Chip Delay: Auto Ch1 Command to CS Delay: Auto Ch2 RDCAS GNT-Chip Delay: Auto Ch2 WRCAS GNT-Chip Delay: Auto Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING) CAS Latency Time (tCL): 5 RAS# to CAS# Delay (tRCD): 5 RAS# Precharge (tRP): 5 Precharge Delay (tRAS): 9 All Precharge to Act: 4 REF to ACT Delay (tRFC): 30 Performance LVL (Read Delay) (tRD): 6 Read delay phase adjust: Enter Ch1 Read delay phase (4~0) - Channel 1 Phase 0 Pull-In: Auto - Channel 1 Phase 1 Pull-In: Auto - Channel 1 Phase 2 Pull-In: Auto - Channel 1 Phase 3 Pull-In: Auto - Channel 1 Phase 4 Pull-In: Auto Ch2 Read delay phase (4~0) - Channel 2 Phase 0 Pull-In: Auto - Channel 2 Phase 1 Pull-In: Auto - Channel 2 Phase 2 Pull-In: Auto - Channel 2 Phase 3 Pull-In: Auto - Channel 2 Phase 4 Pull-In: Auto MCH ODT Latency: AUTO Write to PRE Delay (tWR): 14 Rank Write to Read (tWTR): 11 ACT to ACT Delay (tRRD): 3 Read to Write Delay (tRDWR): 8 Ranks Write to Write (tWRWR): 4 Ranks Read to Read (tRDRD): 5 Ranks Write to Read (tWRRD): 4 Read CAS# Precharge (tRTP): 3 ALL PRE to Refresh: 4
DFI LP LT X38-T2R Bios Settings Code: PC Health Status Adjust CPU Temp: +7C CPU Feature - Thermal Management Control: Disabled - PPM(EIST) Mode: Disabled - Limit CPUID MaxVal: Disabled - CIE Function: Disabled - Execute Disable Bit: Disabled - Virtualization Technology: Disabled - Core Multi-Processing: Enabled Exist Setup Shutdown: Mode 2 Shutdown after AC Loss: Disabled CLOCK VC0 divider: AUTO CPU Clock Ratio Unlock: Enabled CPU Clock Ratio: 9x - Target CPU Clock: 3552 CPU Clock: 390 Boot Up Clock: AUTO DRAM Speed: 266/800 - Target DRAM Speed: 1172 PCIE Clock: 100mhz PCIE Slot Config: 1X 1X CPU Spread Spectrum: Disabled PCIE Spread Spectrum: Disabled SATA Spread Spectrum: Disabled Voltage Settings CPU VID Control: 1.2875 CPU VID Special Add: AUTO DRAM Voltage Control: 2.51 SB Core/CPU PLL Voltage: 1.51 NB Core Voltage: 1.555 CPU VTT Voltage: 1.377 Vcore Droop Control: Enabled Clockgen Voltage Control: 3.45v GTL+ Buffers Strength: Strong Host Slew Rate: Weak GTL REF Voltage Control: Disable x CPU GTL1/3 REF Volt: 110 x CPU GTL 0/2 REF Volt: 110 x North Bridge GTL REF Volt: 110 DRAM Timing - Enhance Data transmitting: FAST - Enhance Addressing: FAST - T2 Dispatch: Enabled Clock Setting Fine Delay Ch1 Clock Crossing Setting: More Aggressive - DIMM 1 Clock fine delay: 4 (manually increased from 3) - DIMM 2 Clock fine delay: 6 (manually set from current 6) - Ch 1 Command fine delay: 11 (manually increased from current 10) - Ch 1 Control fine delay: 7 (manually set from current 7) Ch2 Clock Crossing Setting: More Aggressive - DIMM 3 Clock fine delay: 4 (manually increased from 3) - DIMM 4 Clock fine delay: 6 (manually set from current 6) - Ch 2 Command fine delay: 11 (manually increased from current 10) - Ch 2 Control fine delay: 5 (manually set from current 5) Ch1Ch2 CommonClock Setting: More Aggressive Ch1 RDCAS GNT-Chip Delay: Auto Ch1 WRCAS GNT-Chip Delay: Auto Ch1 Command to CS Delay: Auto Ch2 RDCAS GNT-Chip Delay: Auto Ch2 WRCAS GNT-Chip Delay: Auto Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING) CAS Latency Time (tCL): 4 RAS# to CAS# Delay (tRCD): 4 RAS# Precharge (tRP): 4 Precharge Delay (tRAS): 5 All Precharge to Act: 4 REF to ACT Delay (tRFC): 30 Performance LVL (Read Delay) (tRD): 5 Read delay phase adjust: Enter Ch1 Read delay phase (4~0) - Channel 1 Phase 0 Pull-In: Auto - Channel 1 Phase 1 Pull-In: Auto - Channel 1 Phase 2 Pull-In: Auto - Channel 1 Phase 3 Pull-In: Auto - Channel 1 Phase 4 Pull-In: Auto Ch2 Read delay phase (4~0) - Channel 2 Phase 0 Pull-In: Auto - Channel 2 Phase 1 Pull-In: Auto - Channel 2 Phase 2 Pull-In: Auto - Channel 2 Phase 3 Pull-In: Auto - Channel 2 Phase 4 Pull-In: Auto MCH ODT Latency: AUTO Write to PRE Delay (tWR): 14 Rank Write to Read (tWTR): 11 ACT to ACT Delay (tRRD): 3 Read to Write Delay (tRDWR): 8 Ranks Write to Write (tWRWR): 4 Ranks Read to Read (tRDRD): 5 Ranks Write to Read (tWRRD): 4 Read CAS# Precharge (tRTP): 3 ALL PRE to Refresh: 4 |
| Last edited by eva2000; 20-05-2008 at 06:42 AM. | |
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25-12-2007, 01:08 AM
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| Administrator | Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] Clock Fine Delay At Work Continued.... Swapped out one set of 2x 1GB Crucial Ballistix PC2-8500 for another set of 2x 1GB Crucial Ballistix PC2-8500 since I'm re-testing all my memory on DFI LP LT X38-T2R to find the best matched pair for this board Seems similar process to gain stability occurs with this set too - meaning fine tuning clock fine delay DIMM 1 + 3 as well as controller clock fine delay allows this memory to fly as high if not slightly better than the first set I tested.
DFI LP LT X38-T2R Bios Settings Code: PC Health Status Adjust CPU Temp: +7C CPU Feature - Thermal Management Control: Disabled - PPM(EIST) Mode: Disabled - Limit CPUID MaxVal: Disabled - CIE Function: Disabled - Execute Disable Bit: Disabled - Virtualization Technology: Disabled - Core Multi-Processing: Enabled Exist Setup Shutdown: Mode 2 Shutdown after AC Loss: Disabled CLOCK VC0 divider: AUTO CPU Clock Ratio Unlock: Enabled CPU Clock Ratio: 8x - Target CPU Clock: 3571 CPU Clock: 446 Boot Up Clock: AUTO DRAM Speed: 266/800 - Target DRAM Speed: 1341 PCIE Clock: 100mhz PCIE Slot Config: 1X 1X CPU Spread Spectrum: Disabled PCIE Spread Spectrum: Disabled SATA Spread Spectrum: Disabled Voltage Settings CPU VID Control: 1.2875 CPU VID Special Add: AUTO DRAM Voltage Control: 2.51 SB Core/CPU PLL Voltage: 1.51 NB Core Voltage: 1.630 CPU VTT Voltage: 1.387 Vcore Droop Control: Enabled Clockgen Voltage Control: 3.45v GTL+ Buffers Strength: Strong Host Slew Rate: Weak GTL REF Voltage Control: Disable x CPU GTL1/3 REF Volt: 110 x CPU GTL 0/2 REF Volt: 110 x North Bridge GTL REF Volt: 110 DRAM Timing - Enhance Data transmitting: FAST - Enhance Addressing: FAST - T2 Dispatch: Enabled Clock Setting Fine Delay Ch1 Clock Crossing Setting: More Aggressive - DIMM 1 Clock fine delay: 6 - DIMM 2 Clock fine delay: 6 - Ch 1 Command fine delay: 10 - Ch 1 Control fine delay: 7 Ch2 Clock Crossing Setting: More Aggressive - DIMM 3 Clock fine delay: 6 - DIMM 4 Clock fine delay: 6 - Ch 2 Command fine delay: 10 - Ch 2 Control fine delay: 5 Ch1Ch2 CommonClock Setting: More Aggressive Ch1 RDCAS GNT-Chip Delay: Auto Ch1 WRCAS GNT-Chip Delay: Auto Ch1 Command to CS Delay: Auto Ch2 RDCAS GNT-Chip Delay: Auto Ch2 WRCAS GNT-Chip Delay: Auto Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING) CAS Latency Time (tCL): 5 RAS# to CAS# Delay (tRCD): 5 RAS# Precharge (tRP): 5 Precharge Delay (tRAS): 9 All Precharge to Act: 4 REF to ACT Delay (tRFC): 30 Performance LVL (Read Delay) (tRD): 6 Read delay phase adjust: Enter Ch1 Read delay phase (4~0) - Channel 1 Phase 0 Pull-In: Auto - Channel 1 Phase 1 Pull-In: Auto - Channel 1 Phase 2 Pull-In: Auto - Channel 1 Phase 3 Pull-In: Auto - Channel 1 Phase 4 Pull-In: Auto Ch2 Read delay phase (4~0) - Channel 2 Phase 0 Pull-In: Auto - Channel 2 Phase 1 Pull-In: Auto - Channel 2 Phase 2 Pull-In: Auto - Channel 2 Phase 3 Pull-In: Auto - Channel 2 Phase 4 Pull-In: Auto MCH ODT Latency: AUTO Write to PRE Delay (tWR): 14 Rank Write to Read (tWTR): 11 ACT to ACT Delay (tRRD): 3 Read to Write Delay (tRDWR): 8 Ranks Write to Write (tWRWR): 4 Ranks Read to Read (tRDRD): 5 Ranks Write to Read (tWRRD): 4 Read CAS# Precharge (tRTP): 3 ALL PRE to Refresh: 4 |
| Last edited by eva2000; 20-05-2008 at 06:43 AM. | |
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25-12-2007, 01:08 AM
| #8 (permalink) |
| Administrator | Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly] 2x1GB Crucial Ballistix PC2-8500 Tracer @643Mhz 5-5-5-9 at 2.23v Just having too much fun with clock fine delay tweaking, really brings new life to my Crucial Ballistix PC2-8500 non-Tracer / Tracer memory modules! Swapped in a 3rd kit, this time in dimm slot 2+4 with 2x1GB Cruciall Ballistix PC2-8500 Tracer modules. At first had troubles even with 600Mhz 5-5-5-9 PL6 at 2.19v with memtest86+ v1.70 test #5 having a few errors on 1st pass. Fine tune clock fine delay values and I'm memtesting without problems at 640Mhz 5-5-5-9 PL6 at same 2.19v vdimm ! 645Mhz 5-5-5-9 PL6 took only 2.23v bios set for single Super Pi 32M!!!! This particular set of Ballistix Tracers took 2.4-2.45v to do 651mhz 5-5-5-15 on Asus P5K Deluxe!. DFI LP LT X38-T2R Bios Settings Code: PC Health Status Adjust CPU Temp: +7C CPU Feature - Thermal Management Control: Disabled - PPM(EIST) Mode: Disabled - Limit CPUID MaxVal: Disabled - CIE Function: Disabled - Execute Disable Bit: Disabled - Virtualization Technology: Disabled - Core Multi-Processing: Enabled Exist Setup Shutdown: Mode 2 Shutdown after AC Loss: Disabled CLOCK VC0 divider: AUTO CPU Clock Ratio Unlock: Enabled CPU Clock Ratio: 8x - Target CPU Clock: 3433 CPU Clock: 429 Boot Up Clock: AUTO DRAM Speed: 266/800 - Target DRAM Speed: 1290 PCIE Clock: 100mhz PCIE Slot Config: 1X 1X CPU Spread Spectrum: Disabled PCIE Spread Spectrum: Disabled SATA Spread Spectrum: Disabled Voltage Settings CPU VID Control: 1.2875 CPU VID Special Add: AUTO DRAM Voltage Control: 2.23 SB Core/CPU PLL Voltage: 1.51 NB Core Voltage: 1.591 CPU VTT Voltage: 1.382 Vcore Droop Control: Enabled Clockgen Voltage Control: 3.45v GTL+ Buffers Strength: Strong Host Slew Rate: Weak GTL REF Voltage Control: Disable x CPU GTL1/3 REF Volt: 110 x CPU GTL 0/2 REF Volt: 110 x North Bridge GTL REF Volt: 110 DRAM Timing - Enhance Data transmitting: FAST - Enhance Addressing: FAST - T2 Dispatch: Enabled Clock Setting Fine Delay Ch1 Clock Crossing Setting: More Aggressive - DIMM 1 Clock fine delay: 7 (raised from Current 2) - DIMM 2 Clock fine delay: 7 - Ch 1 Command fine delay: 10 - Ch 1 Control fine delay: 7 Ch2 Clock Crossing Setting: More Aggressive - DIMM 3 Clock fine delay: 7 (raised from Current 2) - DIMM 4 Clock fine delay: 6 - Ch 2 Command fine delay: 10 - Ch 2 Control fine delay: 6 Ch1Ch2 CommonClock Setting: More Aggressive Ch1 RDCAS GNT-Chip Delay: Auto Ch1 WRCAS GNT-Chip Delay: Auto Ch1 Command to CS Delay: Auto Ch2 RDCAS GNT-Chip Delay: Auto Ch2 WRCAS GNT-Chip Delay: Auto Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING) CAS Latency Time (tCL): 5 RAS# to CAS# Delay (tRCD): 5 RAS# Precharge (tRP): 5 Precharge Delay (tRAS): 9 All Precharge to Act: 4 REF to ACT Delay (tRFC): 30 Performance LVL (Read Delay) (tRD): 6 Read delay phase adjust: Enter Ch1 Read delay phase (4~0) - Channel 1 Phase 0 Pull-In: Auto - Channel 1 Phase 1 Pull-In: Auto - Channel 1 Phase 2 Pull-In: Auto - Channel 1 Phase 3 Pull-In: Auto - Channel 1 Phase 4 Pull-In: Auto Ch2 Read delay phase (4~0) - Channel 2 Phase 0 Pull-In: Auto - Channel 2 Phase 1 Pull-In: Auto - Channel 2 Phase 2 Pull-In: Auto - Channel 2 Phase 3 Pull-In: Auto - Channel 2 Phase 4 Pull-In: Auto MCH ODT Latency: AUTO Write to PRE Delay (tWR): 14 Rank Write to Read (tWTR): 11 ACT to ACT Delay (tRRD): 3 Read to Write Delay (tRDWR): 8 Ranks Write to Write (tWRWR): 4 Ranks Read to Read (tRDRD): 5 Ranks Write to Read (tWRRD): 4 Read CAS# Precharge (tRTP): 3 ALL PRE to Refresh: 4 |
| Last edited by eva2000; 20-05-2008 at 06:44 AM. | |
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