DFI Lanparty DK X48-T2RBS Plus bios, info, photos & overclocking tips

05:20 PM

DFI Lanparty DK X48-T2RSB Plus is one of the latest X48 DDR2 based chipsets being offered by DFI. It features some unique technologies which haven't been offered on other DFI motherboards before*.

Some features:

6 layer PCB design
6 phase digital PWM with 18 mosfets*
ABS - Auto Boost System
Intel Overclocking Power Off fixed* - annoyed of the well known power off/recycle process ? Well DFI did away with it completely!
F9 Bios Setup Mode - Advanced and Easy Modes*
Smart Connectors for USB, Firewire board and Front panel headers

DFI Lanparty DK X48-T2RBS Plus photos

Similar to the DFI Lanparty UT X48 series, the northbridge heatsink top half can be removed to cater for other 3rd party northbridge air heatsinks or water cooling blocks. But that's where the similarities end as DFI removed the 3rd party PCI-E x16 slot and 2nd Gigabyte Lan port on the DK X48-T2RSB Plus.
The DK X48-T2RSB Plus manual no longer documents the DFI UT series Ez Clear function where you use Power+Reset buttons in combination to clear CMOS so I assume it's a function not available in DK series. But DFI has added a second Clear CMOS jumper to the back side of the DK X48-T2RSB Plus via a red jumper which is in between the USB ports 6/7 and the Optical S/PDIF out connector as pictured here.

Full photos here

05:46 PM

Downloads & Links

Latest bios

9/23 Official bios

Added F9 Hot Key function.
Fixed ABS function fail when upgrade BIOS
Fixed System cannot display when "two" ATI HD 4870X2 are used in Crossfire.
Update Intel new 45nm CPU micro code.

DK X48-T2RBS Plus Information

Dimm 1+3 Orange slots clock memory slightly better than Dimm 2+4 Yellow slots. Approximately 0.025-0.05v vdimm difference clock for clock.
Clock Generator used = 9LPRS918JKLF (same used by Asus Rampage Extreme according to Legitreviews.com)
Bios is no longer a removal chip, but there's a bios download/flash 7pin header next to the 2nd last PCI slot pictured here.
Differences between DFI DK X48-T2RS vs DFI DK X48-T2RSB Plus

27-10-2008, 03:17 AM #3 (**permalink**)

Bios Template - 9/23 beta bios

Advance Mode

Code:

PC Health Status
Adjust CPU Temp: Auto

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
O.C. Fail retry Counter: 0
O.C. Fail CMOS Reload: Disabled
CPU Clock Ratio: 10x
CPU N/2 Ratio: Disabled
Target CPU Clock: 3330Mhz
CPU Clock: 333
Boot Up Clock: AUTO
CPU Clock Amplitude: 800mv
CPU Clock0 Skew: 0ps
CPU Clock1 Skew: 0ps
DRAM Speed: 333/667
- Target DRAM Speed: DDR2-667
PCIE Clock: 100mhz

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.1750v
CPU VID Special Add: AUT0
DRAM Voltage Control: 1.92v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.465
CPU VTT Voltage: 1.100
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
x MCH RON Offset Value:
x MCH RTT Offset Value:
x MCH Slew Rate Offset Value:
x MCH VREF 1 Value:
x MCH VREF 2 Value: 
x MCH VREF 3 Value:
x CPU GTL 0/2 REF Volt: 0.667X
x CPU GTL 1/3 REF Volt: 0.667X
x North Bridge GTL REF Volt: 0.61X

DRAM Timing
- Enhance Data transmitting: AUTO
- Enhance Addressing: AUTO
- T2 Dispatch: Disabled

Clock Setting Fine Delay
- DRAM CLK Driving Strength: Level 6
- DRAM DATA Driving Strength: Level 8
- Ch1 DLL Default Skew Model: Model 0
- Ch2 DLL Default Skew Model: Model 0

Fine Delay Step Degree: 5ps to 80ps

Ch1 Clock Crossing Setting: AUTO
- DIMM 1 Clock fine delay: Current 2024ps
- DIMM 2 Clock fine delay: Curren 1174ps
- DIMM 2 Control fine delay: Current 1112ps
- DIMM 1 Control fine delay: Current 1112ps
- Ch 1 Command fine delay: Current 74ps

Ch2 Clock Crossing Setting: AUTO
- DIMM 3 Clock fine delay: Current 1900ps
- DIMM 4 Clock fine delay: Current 937ps
- DIMM 4 Control fine delay: Current 886ps
- DIMM 3 Control fine delay: Current 224ps
- Ch 2 Command fine delay: Current 124ps

Ch1Ch2 CommonClock Setting: AUTO

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

Common CMD to CS Timing: 1N/2N/AUTO (command rate)

CAS Latency Time (tCL): 5
RAS# to CAS# Delay (tRCD): 5
RAS# Precharge (tRP): 5
Precharge Delay (tRAS): 18
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO
- Channel 1 Phase 1 Pull-In: AUTO
- Channel 1 Phase 2 Pull-In: AUTO
- Channel 1 Phase 3 Pull-In: AUTO
- Channel 1 Phase 4 Pull-In: AUTO

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

27-10-2008, 03:18 AM #4 (**permalink**)

Bios Screenshots

Latest bios at this time is 9/23 beta bios which adds a F9 Setup Mode option in bios. This option allows you to enable Advance Mode which contains alot more settings to tweak for voltages, memory timings etc. By default Easy Mode is enabled which hides these values.

Easy Mode

Advanced Mode

27-10-2008, 03:18 AM #5 (**permalink**)

System:

E8600 Q820A599 0464
CPU Cooling: Dtek Fuzion Rad Tower Box
DFI LP DK X48-T2RBS Plus - 9/23 beta bios
128MB Gainward FX5200 PCI
2x1GB Teamgroup PC2-10400 dual channel kit
2x1GB Crucial Ballistix PC2-8500 Tracer double sided Micron D9GMH dual channel kit
Memory cooling: 120x25mm Thermaltake 81cfm fan
750GB Samsung SATAII
Pioneer 215 DVD-RW
1200W Silverstone OP1200
WinXP Pro SP2 Nlite Fully Updated.

Initial setup results and findings:

I basically transplanted all my previous setup's gear over to the DK X48-T2RSB Plus while reusing the existing WinXP Pro SP2 OS install left over from DFI LT X38-T2R setup. I decided to push the FSB a bit to see if this DK X48-T2RSB Plus was any better than prior DFI P35/X38/X48 boards I have tried which all seemed to top out at 500-525FSB max for super pi 32M. To my complete surprise, this DK X48-T2RSB Plus was booting into memtest86+ v2.01 and running out of the box at 560-565FSB on 333/667 (1:1) divider with CPU VTT at 1.2v and NB volts at 1.530v! 570FSB was my first hurdle on this board at low volts! That's at least 60FSB better than prior DFI boards I have tried

E8600 Q820A599 @4000Mhz - 10x400FSB

Prime95 v25.6 Load and Post Load Idle

Bios Settings used:

Advance Mode

Code:

PC Health Status
Adjust CPU Temp: -6C

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
O.C. Fail retry Counter: 0
O.C. Fail CMOS Reload: Disabled
CPU Clock Ratio: 10x
CPU N/2 Ratio: Disabled
Target CPU Clock: 4000Mhz
CPU Clock: 400
Boot Up Clock: AUTO
CPU Clock Amplitude: 800mv
CPU Clock0 Skew: 0ps
CPU Clock1 Skew: 0ps
DRAM Speed: 333/667
- Target DRAM Speed: DDR2-667
PCIE Clock: 100mhz

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.21875v
CPU VID Special Add: AUT0
DRAM Voltage Control: 1.925v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.405
CPU VTT Voltage: 1.150
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
x MCH RON Offset Value:
x MCH RTT Offset Value:
x MCH Slew Rate Offset Value:
x MCH VREF 1 Value:
x MCH VREF 2 Value: 
x MCH VREF 3 Value:
x CPU GTL 0/2 REF Volt: 0.667X
x CPU GTL 1/3 REF Volt: 0.667X
x North Bridge GTL REF Volt: 0.61X

DRAM Timing
- Enhance Data transmitting: AUTO
- Enhance Addressing: AUTO
- T2 Dispatch: Disabled

Clock Setting Fine Delay
- DRAM CLK Driving Strength: Level 6
- DRAM DATA Driving Strength: Level 8
- Ch1 DLL Default Skew Model: Model 0
- Ch2 DLL Default Skew Model: Model 0

Fine Delay Step Degree: 5ps to 80ps

Ch1 Clock Crossing Setting: AUTO
- DIMM 1 Clock fine delay: Current 2024ps
- DIMM 2 Clock fine delay: Curren 1174ps
- DIMM 2 Control fine delay: Current 1112ps
- DIMM 1 Control fine delay: Current 1112ps
- Ch 1 Command fine delay: Current 74ps

Ch2 Clock Crossing Setting: AUTO
- DIMM 3 Clock fine delay: Current 1900ps
- DIMM 4 Clock fine delay: Current 937ps
- DIMM 4 Control fine delay: Current 886ps
- DIMM 3 Control fine delay: Current 224ps
- Ch 2 Command fine delay: Current 124ps

Ch1Ch2 CommonClock Setting: AUTO

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

Common CMD to CS Timing: AUTO

CAS Latency Time (tCL): 5
RAS# to CAS# Delay (tRCD): 5
RAS# Precharge (tRP): 5
Precharge Delay (tRAS): 18
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO
- Channel 1 Phase 1 Pull-In: AUTO
- Channel 1 Phase 2 Pull-In: AUTO
- Channel 1 Phase 3 Pull-In: AUTO
- Channel 1 Phase 4 Pull-In: AUTO

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

27-10-2008, 03:19 AM #6 (**permalink**)

Max FSB & Super Pi 32M Comparisons
Untweaked runs

DFI LP DK X48-T2RSB Plus is surprisingly one of the easiest DFI boards to overclock. I decided to leave main timings at 5-5-5-18 and advance memory timings left on AUTO and just find out how the FSB is for untweaked Super Pi 32M runs. Notice how the Performance Level (tRD) value automatically changes when FSB changes. Then I'll revisit tighter timings later on.

Initial first attempt max FSB for single Super Pi 32M ended up around 563FSB and max CPUZ Validation ended up at 571FSB so far. This is already 60+ FSB better than previous DFI boards I have tried!

Max validation @571FSB so far:

Super Pi 32M

10x400FSB 333/667 5-5-5-18 = 12min 41.859s
8x500FSB 333/667 5-5-5-18 = 11min 59.047s
7.5x533FSB 333/667 5-5-5-18 = 11min 50.734s
7x563FSB 333/667 5-5-5-18 = 11min 46.688s

27-10-2008, 03:19 AM #7 (**permalink**)

Memory Overclocking
266/800 (2:3) divider

Quick jump to 2:3 divider memory clocking and like other DFI P35/X38/X48 I've tested up to 650mhz 5-5-5-x is pretty easy with micron D9xxx based DDR2 memory. I spent around 1 hour with 2x1GB Teamgroup PC2-10400 CAS6 memory to hit 701Mhz 5-5-5-18 at 2.675v for max CPUZ Validation with 2x1GB Teamgroup PC2-10400 6-6-6-18 rated memory which is most like Micron D9GMH based. I did save a validation file at 705mhz 5-5-5-18 at 2.675v but it wasn't able to validate with a message to use CPUZ v1.45 to submit instead of 1.48.

I then swapped to 2x1GB Crucial Ballistix PC2-8500 Tracer Micron D9GMH memory and tried the same and managed to hit 705mhz 5-5-5-18 at 2.65v but same error when trying to submit validation, so max 698Mhz 5-5-5-18 at 2.65v for CPUZ Validation and around 668Mhz 5-5-5-18 at 2.65v for Super Pi 32M run.

tRD/Performance level = 7

2x1GB Teamgroup PC2-10400 CAS6 @701Mhz 5-5-5-18 at 2.675v

2x1GB Crucial Ballistix PC2-8500 Tracer Micron D9GMH @698Mhz 5-5-5-18 at 2.65v for CPUZ Validation and around 668Mhz 5-5-5-18 at 2.65v

27-10-2008, 03:20 AM #8 (**permalink**)

Memory Overclocking
333/800 (5:6) divider

Quick comparison look at 7.5x533FSB 5:6 639Mhz 5-5-5-9 at 2.5/2.525v super pi 32M times from straight boot from bios versus memset tweaked run. I ran each configuration first with 2x1GB Teamgroup PC2-10400 CAS6 memory, then with 2x1GB Crucial Ballistix PC2-8500 Tracer memory to see the difference. As you can see while Teamgroup PC2-10400 overall 5-5-5-18 overclocking headroom is ~15-30mhz higher or 0.025-0.05v vdimm better than Crucial Ballistix PC2-8500 Tracer modules, it does come at some cost in clock for clock performance in terms of memory latency as well as Super Pi 32M times.

Teamgroup PC2-10400

Crucial Ballistix PC2-8500 Tracer

Bios Settings used:

Advance Mode

Code:

PC Health Status
Adjust CPU Temp: -6C

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
O.C. Fail retry Counter: 0
O.C. Fail CMOS Reload: Disabled
CPU Clock Ratio: 7.5x
CPU N/2 Ratio: Enabled
Target CPU Clock: 3998Mhz
CPU Clock: 533
Boot Up Clock: AUTO
CPU Clock Amplitude: 800mv
CPU Clock0 Skew: 200ps
CPU Clock1 Skew: 0ps
DRAM Speed: 333/800
- Target DRAM Speed: DDR2-1280
PCIE Clock: 100mhz

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.21875v
CPU VID Special Add: AUT0
DRAM Voltage Control: 2.525v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.665
CPU VTT Voltage: 1.34
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
x MCH RON Offset Value:
x MCH RTT Offset Value:
x MCH Slew Rate Offset Value:
x MCH VREF 1 Value:
x MCH VREF 2 Value: 
x MCH VREF 3 Value:
x CPU GTL 0/2 REF Volt: 0.667X
x CPU GTL 1/3 REF Volt: 0.667X
x North Bridge GTL REF Volt: 0.61X

DRAM Timing
- Enhance Data transmitting: AUTO
- Enhance Addressing: FAST
- T2 Dispatch: Enabled

Clock Setting Fine Delay
- DRAM CLK Driving Strength: Level 1
- DRAM DATA Driving Strength: Level 1 (Team) 2 (Crucial)
- Ch1 DLL Default Skew Model: Model 4
- Ch2 DLL Default Skew Model: Model 4

Fine Delay Step Degree: 5ps to 80ps

Ch1 Clock Crossing Setting: Aggressive
- DIMM 1 Clock fine delay: Current 2024ps
- DIMM 2 Clock fine delay: Curren 1174ps
- DIMM 2 Control fine delay: Current 1112ps
- DIMM 1 Control fine delay: Current 1112ps
- Ch 1 Command fine delay: Current 74ps

Ch2 Clock Crossing Setting: Aggressive
- DIMM 3 Clock fine delay: Current 1900ps
- DIMM 4 Clock fine delay: Current 937ps
- DIMM 4 Control fine delay: Current 886ps
- DIMM 3 Control fine delay: Current 224ps
- Ch 2 Command fine delay: Current 124ps

Ch1Ch2 CommonClock Setting: Aggressive

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

Common CMD to CS Timing: AUTO

CAS Latency Time (tCL): 5
RAS# to CAS# Delay (tRCD): 5
RAS# Precharge (tRP): 5
Precharge Delay (tRAS): 9
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): 26
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: Enabled
- Channel 1 Phase 1 Pull-In: Enabled
- Channel 1 Phase 2 Pull-In: Enabled
- Channel 1 Phase 3 Pull-In: Enabled
- Channel 1 Phase 4 Pull-In: AUTO

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Enabled
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): 4
ALL PRE to Refresh: AUTO