2GB G.Skill F2-8500CL5D-2GBPK - 8 Layer PCB + DFI LT X38-T2R
This is a discussion on 2GB G.Skill F2-8500CL5D-2GBPK - 8 Layer PCB + DFI LT X38-T2R within the DDR2 Intel Memory forums, part of the Intel memory category; Thanks to folks at G.Skill got a new DDR2 kit of memory to play with - 2x1GB G.Skill F2-8500CL5D-2GBPK 8 ...
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12-02-2008, 08:07 PM
| #1 (permalink) |
| Administrator | 2GB G.Skill F2-8500CL5D-2GBPK - 8 Layer PCB + DFI LT X38-T2R
Thanks to folks at G.Skill got a new DDR2 kit of memory to play with - 2x1GB G.Skill F2-8500CL5D-2GBPK 8 layer PCB dual channel kit. All that I have been told is that these use non-Micron D9 ICs but not sure what they use but they seem to perform very well so far     View more images here System
@533Mhz 5-5-5-15 at 2.00v bios (1.93-1.95v Smartguardian)   Click image for larger screenshot Super Pi single & dual 32M   Everest Ultimate Bandwidth & SPD   Prime95 v25.6 Blend Idle & Load   DFI LP LT X38-T2R 1/11 Official Bios Settings Code: PC Health Status Adjust CPU Temp: +9 CPU Feature - Thermal Management Control: Disabled - PPM(EIST) Mode: Disabled - Limit CPUID MaxVal: Disabled - CIE Function: Disabled - Execute Disable Bit: Disabled - Virtualization Technology: Disabled - Core Multi-Processing: Enabled Exist Setup Shutdown: Mode 2 Shutdown after AC Loss: Disabled CLOCK VC0 divider: AUTO CPU Clock Ratio Unlock: Enabled CPU Clock Ratio: 9.5x - Target CPU Clock: 3375 CPU N/2 Ratio: Enabled CPU Clock: 355 Boot Up Clock: AUTO DRAM Speed: 266/800 - Target DRAM Speed: 1067 PCIE Clock: 100mhz PCIE Slot Config: 1X 1X CPU Spread Spectrum: Disabled PCIE Spread Spectrum: Disabled SATA Spread Spectrum: Disabled Voltage Settings CPU VID Control: 1.1875v CPU VID Special Add: AUTO DRAM Voltage Control: 2.00v SB Core/CPU PLL Voltage: 1.51 NB Core Voltage: 1.530 CPU VTT Voltage: 1.200 Vcore Droop Control: Enabled Clockgen Voltage Control: 3.45v GTL+ Buffers Strength: Strong Host Slew Rate: Weak GTL REF Voltage Control: Disable x CPU GTL1/3 REF Volt: 110 x CPU GTL 0/2 REF Volt: 110 x North Bridge GTL REF Volt: 110 DRAM Timing - Enhance Data transmitting: FAST - Enhance Addressing: FAST - T2 Dispatch: Enabled Clock Setting Fine Delay Ch1 Clock Crossing Setting: More Aggressive - DIMM 1 Clock fine delay: Current 89 - DIMM 2 Clock fine delay: Current 456 - DIMM 1 Control fine delay: Current 534 - DIMM 2 Control fine delay: Current 289 - Ch 1 Command fine delay: Current 801 Ch2 Clock Crossing Setting: More Aggressive - DIMM 3 Clock fine delay: Current 89 - DIMM 4 Clock fine delay: Current 400 - DIMM 3 Control fine delay: Current 387 - DIMM 4 Control fine delay: Current 356 - Ch 2 Command fine delay: Current 801 Ch1Ch2 CommonClock Setting: More Aggressive Ch1 RDCAS GNT-Chip Delay: Auto Ch1 WRCAS GNT-Chip Delay: Auto Ch1 Command to CS Delay: Auto Ch2 RDCAS GNT-Chip Delay: Auto Ch2 WRCAS GNT-Chip Delay: Auto Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING) CAS Latency Time (tCL): 5 RAS# to CAS# Delay (tRCD): 5 RAS# Precharge (tRP): 5 Precharge Delay (tRAS): 15 All Precharge to Act: AUTO REF to ACT Delay (tRFC): 42 Performance LVL (Read Delay) (tRD): AUTO Read delay phase adjust: Enter Ch1 Read delay phase (4~0) - Channel 1 Phase 0 Pull-In: AUTO - Channel 1 Phase 1 Pull-In: AUTO - Channel 1 Phase 2 Pull-In: AUTO - Channel 1 Phase 3 Pull-In: AUTO - Channel 1 Phase 4 Pull-In: AUTO Ch2 Read delay phase (4~0) - Channel 2 Phase 0 Pull-In: Auto - Channel 2 Phase 1 Pull-In: Auto - Channel 2 Phase 2 Pull-In: Auto - Channel 2 Phase 3 Pull-In: Auto - Channel 2 Phase 4 Pull-In: Auto MCH ODT Latency: AUTO Write to PRE Delay (tWR): AUTO Rank Write to Read (tWTR): AUTO ACT to ACT Delay (tRRD): AUTO Read to Write Delay (tRDWR): AUTO Ranks Write to Write (tWRWR): AUTO Ranks Read to Read (tRDRD): AUTO Ranks Write to Read (tWRRD): AUTO Read CAS# Precharge (tRTP): AUTO ALL PRE to Refresh: AUTO |
| Last edited by eva2000; 20-05-2008 at 03:53 PM. | |
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13-02-2008, 03:21 AM
| #2 (permalink) |
| Administrator | Re: 2GB G.Skill F2-8500CL5D-2GBPK @600Mhz 5-5-5-15 at 2.10v bios (2.04v Smartguardian)  Click image for larger screenshot Super Pi single & dual 32M   Everest Ultimate Bandwidth  DFI LP LT X38-T2R 1/11 Official Bios Settings Code: PC Health Status Adjust CPU Temp: +9 CPU Feature - Thermal Management Control: Disabled - PPM(EIST) Mode: Disabled - Limit CPUID MaxVal: Disabled - CIE Function: Disabled - Execute Disable Bit: Disabled - Virtualization Technology: Disabled - Core Multi-Processing: Enabled Exist Setup Shutdown: Mode 2 Shutdown after AC Loss: Disabled CLOCK VC0 divider: AUTO CPU Clock Ratio Unlock: Enabled CPU Clock Ratio: 9.5x - Target CPU Clock: 3800 CPU N/2 Ratio: Enabled CPU Clock: 400 Boot Up Clock: AUTO DRAM Speed: 266/800 - Target DRAM Speed: 1203 PCIE Clock: 100mhz PCIE Slot Config: 1X 1X CPU Spread Spectrum: Disabled PCIE Spread Spectrum: Disabled SATA Spread Spectrum: Disabled Voltage Settings CPU VID Control: 1.20000v CPU VID Special Add: AUTO DRAM Voltage Control: 2.10v SB Core/CPU PLL Voltage: 1.51 NB Core Voltage: 1.530 CPU VTT Voltage: 1.205 Vcore Droop Control: Enabled Clockgen Voltage Control: 3.45v GTL+ Buffers Strength: Strong Host Slew Rate: Weak GTL REF Voltage Control: Enable x CPU GTL1/3 REF Volt: 79 x CPU GTL 0/2 REF Volt: 79 x North Bridge GTL REF Volt: 79 DRAM Timing - Enhance Data transmitting: FAST - Enhance Addressing: FAST - T2 Dispatch: Enabled Clock Setting Fine Delay Ch1 Clock Crossing Setting: More Aggressive - DIMM 1 Clock fine delay: 280 - DIMM 2 Clock fine delay: 420 - DIMM 1 Control fine delay: 560 - DIMM 2 Control fine delay: 280 - Ch 1 Command fine delay: 770 Ch2 Clock Crossing Setting: More Aggressive - DIMM 3 Clock fine delay: 280 - DIMM 4 Clock fine delay: 420 - DIMM 3 Control fine delay: 560 - DIMM 4 Control fine delay: 280 - Ch 2 Command fine delay: 770 Ch1Ch2 CommonClock Setting: More Aggressive Ch1 RDCAS GNT-Chip Delay: Auto Ch1 WRCAS GNT-Chip Delay: Auto Ch1 Command to CS Delay: Auto Ch2 RDCAS GNT-Chip Delay: Auto Ch2 WRCAS GNT-Chip Delay: Auto Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING) CAS Latency Time (tCL): 5 RAS# to CAS# Delay (tRCD): 5 RAS# Precharge (tRP): 5 Precharge Delay (tRAS): 15 All Precharge to Act: AUTO REF to ACT Delay (tRFC): 42 Performance LVL (Read Delay) (tRD): AUTO Read delay phase adjust: Enter Ch1 Read delay phase (4~0) - Channel 1 Phase 0 Pull-In: AUTO - Channel 1 Phase 1 Pull-In: AUTO - Channel 1 Phase 2 Pull-In: AUTO - Channel 1 Phase 3 Pull-In: AUTO - Channel 1 Phase 4 Pull-In: AUTO Ch2 Read delay phase (4~0) - Channel 2 Phase 0 Pull-In: Auto - Channel 2 Phase 1 Pull-In: Auto - Channel 2 Phase 2 Pull-In: Auto - Channel 2 Phase 3 Pull-In: Auto - Channel 2 Phase 4 Pull-In: Auto MCH ODT Latency: AUTO Write to PRE Delay (tWR): AUTO Rank Write to Read (tWTR): AUTO ACT to ACT Delay (tRRD): AUTO Read to Write Delay (tRDWR): AUTO Ranks Write to Write (tWRWR): AUTO Ranks Read to Read (tRDRD): AUTO Ranks Write to Read (tWRRD): AUTO Read CAS# Precharge (tRTP): AUTO ALL PRE to Refresh: AUTO |
| Last edited by eva2000; 20-05-2008 at 03:54 PM. | |
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13-02-2008, 03:25 AM
| #3 (permalink) |
| Administrator | Re: 2GB G.Skill F2-8500CL5D-2GBPK CAS4 Results Looks like 490mhz 4-4-4-12 is the limit at 2.19v bios set vdimm. Setting CAS5 as in 5-4-4-12/15 didn't help but it could do 5-5-4-x easily at higher clocks. 2.23-2.27v vdimm allowed less memtest86+ v2.00 errors but still were a few when looping test #5. @490Mhz 4-4-4-12 at 2.19v bios set  Super Pi single & dual 32M - Including Everest Bandwidth   DFI LP LT X38-T2R 1/11 Official Bios Settings Code: PC Health Status Adjust CPU Temp: +9 CPU Feature - Thermal Management Control: Disabled - PPM(EIST) Mode: Disabled - Limit CPUID MaxVal: Disabled - CIE Function: Disabled - Execute Disable Bit: Disabled - Virtualization Technology: Disabled - Core Multi-Processing: Enabled Exist Setup Shutdown: Mode 2 Shutdown after AC Loss: Disabled CLOCK VC0 divider: AUTO CPU Clock Ratio Unlock: Enabled CPU Clock Ratio: 9.5x - Target CPU Clock: 3102 CPU N/2 Ratio: Enabled CPU Clock: 326 Boot Up Clock: AUTO DRAM Speed: 266/800 - Target DRAM Speed: 980 PCIE Clock: 100mhz PCIE Slot Config: 1X 1X CPU Spread Spectrum: Disabled PCIE Spread Spectrum: Disabled SATA Spread Spectrum: Disabled Voltage Settings CPU VID Control: 1.1875v CPU VID Special Add: AUTO DRAM Voltage Control: 2.19v SB Core/CPU PLL Voltage: 1.51 NB Core Voltage: 1.530 CPU VTT Voltage: 1.200 Vcore Droop Control: Enabled Clockgen Voltage Control: 3.45v GTL+ Buffers Strength: Strong Host Slew Rate: Weak GTL REF Voltage Control: Disable x CPU GTL1/3 REF Volt: 110 x CPU GTL 0/2 REF Volt: 110 x North Bridge GTL REF Volt: 110 DRAM Timing - Enhance Data transmitting: FAST - Enhance Addressing: FAST - T2 Dispatch: Enabled Clock Setting Fine Delay Ch1 Clock Crossing Setting: More Aggressive - DIMM 1 Clock fine delay: 350 - DIMM 2 Clock fine delay: 560 - DIMM 1 Control fine delay: 560 - DIMM 2 Control fine delay: 420 - Ch 1 Command fine delay: 980 Ch2 Clock Crossing Setting: More Aggressive - DIMM 3 Clock fine delay: 350 - DIMM 4 Clock fine delay: 560 - DIMM 3 Control fine delay: 560 - DIMM 4 Control fine delay: 420 - Ch 2 Command fine delay: 980 Ch1Ch2 CommonClock Setting: More Aggressive Ch1 RDCAS GNT-Chip Delay: Auto Ch1 WRCAS GNT-Chip Delay: Auto Ch1 Command to CS Delay: Auto Ch2 RDCAS GNT-Chip Delay: Auto Ch2 WRCAS GNT-Chip Delay: Auto Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING) CAS Latency Time (tCL): 4 RAS# to CAS# Delay (tRCD): 4 RAS# Precharge (tRP): 4 Precharge Delay (tRAS): 12 All Precharge to Act: AUTO REF to ACT Delay (tRFC): 42 Performance LVL (Read Delay) (tRD): 5 Read delay phase adjust: Enter Ch1 Read delay phase (4~0) - Channel 1 Phase 0 Pull-In: AUTO - Channel 1 Phase 1 Pull-In: AUTO - Channel 1 Phase 2 Pull-In: AUTO - Channel 1 Phase 3 Pull-In: AUTO - Channel 1 Phase 4 Pull-In: AUTO Ch2 Read delay phase (4~0) - Channel 2 Phase 0 Pull-In: Auto - Channel 2 Phase 1 Pull-In: Auto - Channel 2 Phase 2 Pull-In: Auto - Channel 2 Phase 3 Pull-In: Auto - Channel 2 Phase 4 Pull-In: Auto MCH ODT Latency: AUTO Write to PRE Delay (tWR): AUTO Rank Write to Read (tWTR): AUTO ACT to ACT Delay (tRRD): AUTO Read to Write Delay (tRDWR): AUTO Ranks Write to Write (tWRWR): AUTO Ranks Read to Read (tRDRD): AUTO Ranks Write to Read (tWRRD): AUTO Read CAS# Precharge (tRTP): AUTO ALL PRE to Refresh: AUTO |
| Last edited by eva2000; 20-05-2008 at 03:54 PM. | |
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