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Barely a week into the introduction of the DDR3-supportive AM3 socket CPUs, the processors seem to be having design flaws. This, as circulated by AMD in its revision guide document for the 10h family of processors (found here, page 80). The issue, as described by AMD, centers around the DDR3 memory sub-system. On machines with more than one PC3-10600 (1333 MHz) memory module populating a memory channel, the users may experience unreliable operation. The company does not get into the specifics of the symptoms. This issue however, does not affect systems with a module per channel (one or two modules installed in the motherboard), and only those with three to four modules installed.

The AMD K10 memory controllers on AM3-socket processor provide a 128-bit wide memory interface (with DRAM Ganged mode enabled), which amount to two 64-bit wide memory channels. On most motherboards, four DIMM slots with two slots sharing a memory channel are present. With this issue, one is not recommended to use more than one DDR3-1333 memory module per channel. AMD recommends a quick fix for the issue for systems using more than one DDR3-1333 module per memory channel: to manually specify the memory to run at 533 MHz (1066 MHz DDR), and accordingly set DRAM timings. As a little compensation, one can tighten DRAM timings with the drop in frequency. AMD will fix this issue in the next stepping (sub-version) of the CPUs. The "x-factor" with this erratum revolves around DRAM voltage, a significant factor. One might note AMD saying "the processor memory subsystem may exhibit unreliable operation over the allowable VDDIO voltage range", which leads us to think if there is a potential workaround with adjusting the DRAM voltage beyond the allowable range (read: over-volting the memory). We hope to hear more from AMD on this.



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