PC Health Status
Adjust CPU Temp: Auto

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
O.C. Fail retry Counter: 0
O.C. Fail CMOS Reload: Disabled
CPU Clock Ratio: 10x
CPU N/2 Ratio: Disabled
Target CPU Clock: 3330Mhz
CPU Clock: 333
Boot Up Clock: AUTO
CPU Clock Amplitude: 800mv
CPU Clock0 Skew: 0ps
CPU Clock1 Skew: 0ps
DRAM Speed: 333/667
- Target DRAM Speed: DDR2-667
PCIE Clock: 100mhz

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.1750v
CPU VID Special Add: AUT0
DRAM Voltage Control: 1.92v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.465
CPU VTT Voltage: 1.100
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
x MCH RON Offset Value:
x MCH RTT Offset Value:
x MCH Slew Rate Offset Value:
x MCH VREF 1 Value:
x MCH VREF 2 Value: 
x MCH VREF 3 Value:
x CPU GTL 0/2 REF Volt: 0.667X
x CPU GTL 1/3 REF Volt: 0.667X
x North Bridge GTL REF Volt: 0.61X

DRAM Timing
- Enhance Data transmitting: AUTO
- Enhance Addressing: AUTO
- T2 Dispatch: Disabled

Clock Setting Fine Delay
- DRAM CLK Driving Strength: Level 6
- DRAM DATA Driving Strength: Level 8
- Ch1 DLL Default Skew Model: Model 0
- Ch2 DLL Default Skew Model: Model 0

Fine Delay Step Degree: 5ps to 80ps

Ch1 Clock Crossing Setting: AUTO
- DIMM 1 Clock fine delay: Current 2024ps
- DIMM 2 Clock fine delay: Curren 1174ps
- DIMM 2 Control fine delay: Current 1112ps
- DIMM 1 Control fine delay: Current 1112ps
- Ch 1 Command fine delay: Current 74ps

Ch2 Clock Crossing Setting: AUTO
- DIMM 3 Clock fine delay: Current 1900ps
- DIMM 4 Clock fine delay: Current 937ps
- DIMM 4 Control fine delay: Current 886ps
- DIMM 3 Control fine delay: Current 224ps
- Ch 2 Command fine delay: Current 124ps

Ch1Ch2 CommonClock Setting: AUTO

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

Common CMD to CS Timing: 1N/2N/AUTO (command rate)

CAS Latency Time (tCL): 5
RAS# to CAS# Delay (tRCD): 5
RAS# Precharge (tRP): 5
Precharge Delay (tRAS): 18
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): AUTO
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO
- Channel 1 Phase 1 Pull-In: AUTO
- Channel 1 Phase 2 Pull-In: AUTO
- Channel 1 Phase 3 Pull-In: AUTO
- Channel 1 Phase 4 Pull-In: AUTO

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO