5:6 Memory Divider (2.40B) + MCH Tweak Testing

Revisiting the 2.40B 5:6 memory divider but this time I've gotten a better handle on tweaking memory, voltages and the above outlined MCH tweaks

I had no problems using NB (MCH) voltage of 1.56v for these tests which helped stablise the high 640Mhz 5-5-5-15 memory clock along with what P45 chipset considers tight tRead value of 9.

Setting the 4 subtimings listed here to the following also helped stablise memory clock at 640mhz 5-5-5-15 at 2.56v

• Trd2rd(Different Rank).: 10
• Twr2wr(Different Rank): 9
• Twr2rd(Different Rank): 9
• Trd2wr(Same/Diff Rank): 10

7.5x533FSB 2.40B 640Mhz 5-5-5-15

tRD 9


tRD 9 + Tweak 1


tRD 9 + Tweak 1 + 2


Super Pi 1M with Tweak 1 + 2


Super Pi 32M with Tweak 1 + 2


32M time still around 20-25 seconds slower than P35/X38/X48 but getting there