DFI LP UT X48-T3RS - Info, overclocking tips & photos

11:52 AM

6/9 Beta bios - Memory testing

DFI released a 6/9 beta bios which is meant to improve memory overclocking. Visually not many changes compared to 6/4 beta bios except the removal of 6 of the MCH GTL ref options. With 6/9 beta bios I can't hit 8x500FSB 400/1600 DDR3-2000Mhz at all = no boot - on 6/4 TTTT.bin beta bios I could using model 3 though. I tried all 4 models from 0 to 3 and none allow me to boot at 8x500 400/600 on 6/9 beta bios.

However, 6/9 beta bios has improved memory overclocking in general especially on 7-7-7-x timings. I managed to complete both single Super Pi 32M and dual Super Pi 32M via HyperPi gui wrapper app @934Mhz 7-7-7-18 1T at 2.15v again DRAM Default Skew model 3 helped stabilize my Micron D9 IC based 2x1GB OCZ PC3-14400 Platinum kit along with a slight adjustment for DIMM 4 Clock fine delay changing it from Current 462ps to 22 DEG 550ps with a Fine Delay Step Degree value of 25ps (22x25ps = 550ps)

@934Mhz 7-7-7-18 1T at 2.15v

Result:

Super Pi 32M single = 12m 11.016s
Dual Super Pi 32M average time = 13m 45.093s
Everest Ultimate Bandwidth read/write/copy/latency = 11326 / 9941 / 10249 / 47.1ns

@940Mhz 7-7-7-18 1T at 2.15v

Bit higher at same 2.15v vdimm. Nearly pulled off 950Mhz 7-7-7-18 1T at 2.15v but errored out half way into Super Pi 32M

Result:

Super Pi 32M = 12m 04.734s

DFI LP UT X48-T3RS Bios Settings

6/9 beta bios

Code:

PC Health Status
Adjust CPU Temp: Auto

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
O.C. Fail retry Counter 0
CPU Clock Ratio: 8x
CPU N/2 Ratio: Disabled
Target CPU Clock: 3736
CPU Clock: 467
Boot Up Clock: AUTO
CPU Clock Amplitude: 800mv
CPU Clock0 Skew: 200ps
CPU Clock1 Skew: 200ps
DRAM Speed: 400/1600
- Target DRAM Speed: DDR3-1868
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.250v
COY VID Special Add Limit: Enabled
CPU VID Special Add: AUT0
DRAM Voltage Control: 2.15v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.677
CPU VTT Voltage: 1.240
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL 1/2 REF Volt: 113
x CPU GTL 0/3 REF Volt: 100
x North Bridge GTL REF Volt: 100

DRAM Timing
- Enhance Data transmitting: Auto
- Enhance Addressing: Auto
- T2 Dispatch: Auto

DRAM Default Skew Model: Model 3

Fine Delay Step Degree: 25ps

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: AUTO
- DIMM 1 Clock fine delay: Current 350ps
- DIMM 2 Clock fine delay: Curren 350ps
- DIMM 2 Control fine delay: Current 385ps
- DIMM 1 Control fine delay: Current 385ps
- Ch 1 Command fine delay: Current 203ps

Ch2 Clock Crossing Setting: AUTO
- DIMM 3 Clock fine delay: Current 462ps
- DIMM 4 Clock fine delay: 22 DEG 550ps
- DIMM 4 Control fine delay: Current 490ps
- DIMM 3 Control fine delay: Current 490ps
- Ch 2 Command fine delay: Current 315ps

Ch1Ch2 CommonClock Setting: AUTO

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

Common CMD to CS Timing: Auto = 1T

CAS Latency Time (tCL): 7
RAS# to CAS# Delay (tRCD): 7
RAS# Precharge (tRP): 7
Precharge Delay (tRAS): 18
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): 56
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO
- Channel 1 Phase 1 Pull-In: AUTO
- Channel 1 Phase 2 Pull-In: AUTO
- Channel 1 Phase 3 Pull-In: AUTO
- Channel 1 Phase 4 Pull-In: AUTO

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

@950Mhz 7-7-7-18 1T at 2.22v

Bumped voltages up but kept timings all the same for DDR3-1900Mhz 7-7-7-18 1T at 2.22v for single Super Pi 32M run

Results

Super Pi 32M = 11m 58.156s
Everest Ultimate Bandwidth read/write/copy/latency = 11452 / 10110 / 10311 / 46.5ns

DFI LP UT X48-T3RS Bios Settings

6/9 beta bios

Code:

PC Health Status
Adjust CPU Temp: Auto

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
O.C. Fail retry Counter 0
CPU Clock Ratio: 8x
CPU N/2 Ratio: Disabled
Target CPU Clock: 3802
CPU Clock: 475
Boot Up Clock: AUTO
CPU Clock Amplitude: 800mv
CPU Clock0 Skew: 300ps
CPU Clock1 Skew: 300ps
DRAM Speed: 400/1600
- Target DRAM Speed: DDR3-1900
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.2750v
COY VID Special Add Limit: Enabled
CPU VID Special Add: AUT0
DRAM Voltage Control: 2.22v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.677
CPU VTT Voltage: 1.270
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL 1/2 REF Volt: 113
x CPU GTL 0/3 REF Volt: 100
x North Bridge GTL REF Volt: 100

DRAM Timing
- Enhance Data transmitting: Auto
- Enhance Addressing: Auto
- T2 Dispatch: Auto

DRAM Default Skew Model: Model 3

Fine Delay Step Degree: 25ps

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: AUTO
- DIMM 1 Clock fine delay: Current 350ps
- DIMM 2 Clock fine delay: Curren 350ps
- DIMM 2 Control fine delay: Current 385ps
- DIMM 1 Control fine delay: Current 385ps
- Ch 1 Command fine delay: Current 203ps

Ch2 Clock Crossing Setting: AUTO
- DIMM 3 Clock fine delay: Current 462ps
- DIMM 4 Clock fine delay: 22 DEG 550ps
- DIMM 4 Control fine delay: Current 490ps
- DIMM 3 Control fine delay: Current 490ps
- Ch 2 Command fine delay: Current 315ps

Ch1Ch2 CommonClock Setting: AUTO

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto

Common CMD to CS Timing: Auto = 1T

CAS Latency Time (tCL): 7
RAS# to CAS# Delay (tRCD): 7
RAS# Precharge (tRP): 7
Precharge Delay (tRAS): 18
All Precharge to Act: AUTO
REF to ACT Delay (tRFC): 56
Performance LVL (Read Delay) (tRD): AUTO

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: AUTO
- Channel 1 Phase 1 Pull-In: AUTO
- Channel 1 Phase 2 Pull-In: AUTO
- Channel 1 Phase 3 Pull-In: AUTO
- Channel 1 Phase 4 Pull-In: AUTO

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): AUTO
Rank Write to Read (tWTR): AUTO
ACT to ACT Delay (tRRD): AUTO
Read to Write Delay (tRDWR): AUTO
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): AUTO
ALL PRE to Refresh: AUTO

@1002Mhz 7-7-7-18 1T at 2.22v

Boot from 950Mhz 7-7-7-18 1T at 2.22v and setFSB my way up to max CPUZ Validation of DDR3-2004Mhz 1T at 2.22v

Result:
Max CPUZ Validation = 1002Mhz 7-7-7-18 1T at 2.22v