DFI LP LT X38-T2R 1/11 Bios Settings

PC Health Status
Adjust CPU Temp: +6

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 10x
- Target CPU Clock: 3973
N/2 Ratio: Disabled
CPU Clock: 397
Boot Up Clock: AUTO
DRAM Speed: 266/800
- Target DRAM Speed: 1193
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.3375v
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.23v
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.555
CPU VTT Voltage: 1.175
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Enable
x CPU GTL1/3 REF Volt: 105
x CPU GTL 0/2 REF Volt: 97
x North Bridge GTL REF Volt: 82

DRAM Timing
- Enhance Data transmitting: FAST 
- Enhance Addressing: AUTO
- T2 Dispatch: Disabled 

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: More Aggressive
- DIMM 1 Clock fine delay: 420
- DIMM 2 Clock fine delay: 560
- DIMM 1 Control fine delay: 560
- DIMM 2 Control fine delay: 420
- Ch 1 Command fine delay: 910

Ch2 Clock Crossing Setting: More Aggressive
- DIMM 3 Clock fine delay: 420
- DIMM 4 Clock fine delay: 560
- DIMM 3 Control fine delay: 560
- DIMM 4 Control fine delay: 420
- Ch 2 Command fine delay: 910

Ch1Ch2 CommonClock Setting: More Aggressive

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)

CAS Latency Time (tCL): 5
RAS# to CAS# Delay (tRCD): 5
RAS# Precharge (tRP): 5
Precharge Delay (tRAS): 15
All Precharge to Act: Auto
REF to ACT Delay (tRFC): 60
Performance LVL (Read Delay) (tRD): 6

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: Auto
- Channel 1 Phase 1 Pull-In: Enabled
- Channel 1 Phase 2 Pull-In: Enabled
- Channel 1 Phase 3 Pull-In: Enabled
- Channel 1 Phase 4 Pull-In: Enabled

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Enabled
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: Auto
Write to PRE Delay (tWR): 14
Rank Write to Read (tWTR): 11
ACT to ACT Delay (tRRD): Auto
Read to Write Delay (tRDWR): Auto
Ranks Write to Write (tWRWR): Auto
Ranks Read to Read (tRDRD): Auto
Ranks Write to Read (tWRRD): Auto
Read CAS# Precharge (tRTP): Auto
ALL PRE to Refresh: Auto