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View Single Post - DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly]
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Old 25-12-2007, 01:09 AM   #9 (permalink)
eva2000
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Re: DFI Lanparty LT X38-T2R - Info, overclocking tips & photos [56k user friendly]

2x1GB Crucial Ballistix PC2-8500 Tracer @659Mhz 5-5-5-9 at 2.38v


Even better, 640mhz 5-5-5-9 at 2.19v, 643mhz 5-5-5-9 at 2.23v and now 659mhz 5-5-5-9 at 2.38v !

DFI LP LT X38-T2R Bios Settings


Code:
PC Health Status
Adjust CPU Temp: +7C

CPU Feature
- Thermal Management Control: Disabled
-  PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 8x
- Target CPU Clock: 3515
CPU Clock: 439
Boot Up Clock: AUTO
DRAM Speed: 266/800
- Target DRAM Speed: 1320
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.2875
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.38
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.604
CPU VTT Voltage: 1.387
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: FAST
- Enhance Addressing: FAST
- T2 Dispatch: Enabled 

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: More Aggressive
- DIMM 1 Clock fine delay: 7 (raised from Current 2)
- DIMM 2 Clock fine delay: 7
- Ch 1 Command fine delay: 10
- Ch 1 Control fine delay: 7


Ch2 Clock Crossing Setting: More Aggressive
- DIMM 3 Clock fine delay: 7 (raised from Current 2)
- DIMM 4 Clock fine delay: 6
- Ch 2 Command fine delay: 10
- Ch 2 Control fine delay: 6

Ch1Ch2 CommonClock Setting: More Aggressive

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)

CAS Latency Time (tCL): 5
RAS# to CAS# Delay (tRCD): 5
RAS# Precharge (tRP): 5
Precharge Delay (tRAS): 9
All Precharge to Act: 4
REF to ACT Delay (tRFC): 30
Performance LVL (Read Delay) (tRD): 6

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: Auto 
- Channel 1 Phase 1 Pull-In: Auto
- Channel 1 Phase 2 Pull-In: Auto
- Channel 1 Phase 3 Pull-In: Auto
- Channel 1 Phase 4 Pull-In: Auto

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): 14
Rank Write to Read (tWTR): 11
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 4
Ranks Read to Read (tRDRD): 5
Ranks Write to Read (tWRRD): 4
Read CAS# Precharge (tRTP): 3
ALL PRE to Refresh: 4

Last edited by eva2000; 20-05-2008 at 06:44 AM.
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