Now trying to combine max memory overclocks with max cpu clocks with HT disabled, but seems I'm being held back by possibly 2 factors
- Xeon W3540 3845B010 cpu temps which at 4660Mhz at 1.528-1.544v was already idling at same temps of 46-52C as my Super Pi 32M run with Xeon W3520 3845A935 was @4794Mhz at 1.552v with exact same H20 cooling.
- Memory clocks didn't seem to be as stable as tested at lower cpu clocks, probably due to cpu heat affecting memory stability ? Going to work on the voltages etc to see.
In meantime, here's what I could pull off @4660Mhz HT Disabled 32M Pi at 1.528v and validation @4812Mhz at 1.544v (limited by mem clock).
System: Max Validation
Limited by mem stability/clock due to cpu heat ?
Max Super Pi 32M @4660Mhz at 1.528v
Took a side by side screenshot of my 12x mem multi DDR3-2184Mhz 7-8-7-20 1T 32M run versus my 10x mem multi higher cpu clocked DDR3-2118Mhz 7-8-7-20 1T 32M run to see what cputweaker reported for my subtimings. See if any subtiming settings are a factor.
DDR3-2184Mhz (12x mem) vs DDR3-2118Mhz (10x mem) - QPI/DRAM volts = 1.55v vs 1.6375v due to lower bclk needed on 12x mem config
- tRFC = 110 vs 88 could be a factor ?
- tRRD = 7 vs 7 both same
- tREFI = 955 vs 849
- tFAW = 37 vs 33
- tRTL A channel = 56 vs 57
- tWTP = 27 vs 26
- tRTP = 7 vs 6
- Write to Read (same rank) = 20 vs 19
Going to play with subtimings and see
Update: Dropped cpu multiplier to 19x and using 10x memory multiplier, will try to reproduce similar looser subtimings as used in my
DDR3-2184Mhz 7-8-7-20 1T run with 12x memory multiplier. I managed to get as far as Super Pi 32M stable @DDR3-2188Mhz 7-8-7-20 1T at 1.84v
vdimm
Manually set following subtiming values in bios:
- tRFC = 110
- tFAW = 37
- Back to Back CAS# Delay = 4 (tightened to try and offset loosened tRFC value)
- Write to Read (same rank) = 20
Super Pi 32M passed at: DDR3-2158Mhz 7-8-7-20 1T at 1.72v
DDR3-2167Mhz 7-8-7-20 1T at 1.78v
DDR3-2177Mhz 7-8-7-20 1T at 1.80v
DDR3-2188Mhz 7-8-7-20 1T at 1.84v
