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09-06-2009, 03:50 AM
#3 (permalink)
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Yeah very unfortunate as I really was hoping #3 would be matching #2 for 1000mhz possibilities in dual channel
Interesting starting dual channel with module #1 (B2) + #2 (A2 banks) and at DDR3-1600 8-8-8-24 already memtest reports 5,878MB bandwidth but dozen or so test #5 errors but loosening the 4 above sub timings help reduced the errors somewhat so far to 1 or 2 errors per pass.
- tRTR_S= 4 change to 6
- tRTR_D = 7 change to 9
- tWTW_S = 4 change to 6
- tWTW_D = 7 change to 9
resulting bandwidth is still 5,878MB/s in dual channel so room to move i think for stbaility. Changing tRTR_S and tWTW_S to 7 dropped bandwidth to 5,691MB/s
Seems advancing skews for both A2/B2 CLK Skew to 150ps and 200ps respectively along with 8-9-8-9 for subtimings and NB DDRVREF at -17.5mv have me error free looping test #5 (each pass for 2x2GB config takes 130 seconds to complete) - did 10 pass loop without errors. Huge difference to 1000s of errors without CLK skew tweaking! Memtest reported bandwidth still at 5,691MB/s ! Starting tests at DDR3-1700Mhz 8-8-8-24 and error free so far.. without touching any voltages for memory or NB yet!